Hi,
We are using AFE5809 in the test pattern mode to test our system performance. We would like to have more information on the test pattern. Can you please let us know in the toggle mode how many clock cycle will it take to change from all 1s to all 0s. Thank you very much.
Best,
Po
Hi,
My customer is considering to apply a heat sink to AFE5812.
This is not thermal question at all, but it is mechanical one.
Do you have any weight restrictions for heat sink ?
In other words, how much pressure could be allowed to the package top for the operating condition ?
I could not find such information in datasheet and thermal design guide.
If you have the specifications for this, please let me know.
Best Regards,
itabi
Hi,
I'm interested in testing the VSP5610, but there isn't an evaluation board available. Is there one in development, or an example schematic available? If not, can you suggest a reference schematic that I can use as a starting point? Thank you!
Jonathan
Hey team,
I am attaching the datasheet for a CCD being used in an end application (the CCD30-11 Back Illuminated CCD Sensor). TI of course has many AFE devices that can be used to read out a CCD, but we're having trouble identifying the best EVM for this device.
Could you please point me towards a suitable EVM which we offer?
Thanks!
-Kareem Moulana
(Please visit the site to view this file)
Hi TI people,
Can you help us design a set of filter coefficients to program into our AFE5809's Filter Coefficient RAM?
If possible, can you provide the coefficients for 32/16=2Mhz, 32/32 =1MHz and 32/64=0.5 MHz LPF filter frequency (Anti-aliasing band is half of sampling frequency).
Will I need three profiles in Profile RAM to point to these three sets of Coefficients?
If you need any more information from us, please just ask.
Thanks,
Duncan Hurst
Dear Sirs
Does TI provide Photo sensor/diode like attachment?
(Please visit the site to view this file)
BRS
Nat
HI,
I am currently trying to propose an imaging analog front-end device for use in the facsimile equipment to the customer.
Imaging sensor to use in the facsimile equipment of the customer is DL100-05EUJS-3.
DL100-05EUJS-3 : 200 DPI A4 size contact image sensor spec
1. Product Description
Number Of Sensor Elements : 1728(1 to 1712 dots available)
Resolution : 200 DPI
Scanning speed : 5 msec/line
Light Source : Wavelength 570 nm
Data Output : 1 Analogue
2. Electrical Characteristics
Power Supply (VDD) 3.0V(min) 3.3V(typ) 3.6V(max)
Input CLK Voltage (VIH) SI & CLK 2.1V(min)
Input CLK Voltage (VIL) SI & CLK 1.08V(max)
Input CLK Current (IIH) SI & CLK 500uA(max)
Input CLK Current (IIL) SI & CLK -0.2mA(max)
CLK Frequency (Fmax) 0.5MHz(typ) 0.77MHz(max)
Clock Duty (tw/to) 75%(typ)
For reference, we will describe a similar product data sheet of the linked VDD = 5V specification.
pdf.datasheetarchive.com/.../DSA00402546.pdf
The demand for imaging analog front-end device from customers.
· Timing Generator is built
· CMOS output
I have some questions about AFE.
Q1: The VSP5610 data sheet of the model number that I heard from the customer, there is no description of the CIS (contact image sensor).
Can we use this CIS in the VSP5610 device?
Q2: RLCK of the VSP5610 is 1MHz(min). (datasheet 3-page)
Clock frequency of this CIS is 0.77MHz(max).
Do you have a track record that corresponds with an external frequency divider circuit in order to lower this CIS clock frequency in the VSP5610?
Q3: Do the MODE3 of LM98714 or LM98722 be used to the CIS(Mono color)?
Q4: Do you have a track record that corresponds with an external frequency divider circuit in order to lower this CIS clock frequency in the MODE1 of LM98714 or LM98722?
Q5：Are there any other imaging analog front-end devices that the CIS can use?
Please send me the informations.
Best Regards
H.Masumoto
HI,
I am currently trying to propose an imaging analog front-end device for use in the facsimile equipment to the customer.
Imaging sensor to use in the facsimile equipment of the customer is DL100-05EUJS-3.
DL100-05EUJS-3 : 200 DPI A4 size contact image sensor spec
1. Product Description
Number Of Sensor Elements : 1728(1 to 1712 dots available)
Resolution : 200 DPI
Scanning speed : 5 msec/line
Light Source : Wavelength 570 nm
Data Output : 1 Analogue
2. Electrical Characteristics
Power Supply (VDD) 3.0V(min) 3.3V(typ) 3.6V(max)
Input CLK Voltage (VIH) SI & CLK 2.1V(min)
Input CLK Voltage (VIL) SI & CLK 1.08V(max)
Input CLK Current (IIH) SI & CLK 500uA(max)
Input CLK Current (IIL) SI & CLK -0.2mA(max)
CLK Frequency (Fmax) 0.5MHz(typ) 0.77MHz(max)
Clock Duty (tw/to) 75%(typ)
For reference, we will describe a similar product data sheet of the linked VDD = 5V specification.
pdf.datasheetarchive.com/.../DSA00402546.pdf
The demand for imaging analog front-end device from customers.
· Timing Generator is built
· CMOS output
I have some questions about AFE.
Q1: The VSP5610 data sheet of the model number that I heard from the customer, there is no description of the CIS (contact image sensor).
Can we use this CIS in the VSP5610 device?
Q2: RLCK of the VSP5610 is 1MHz(min). (datasheet 3-page)
Clock frequency of this CIS is 0.77MHz(max).
Do you have a track record that corresponds with an external frequency divider circuit in order to lower this CIS clock frequency in the VSP5610?
Q3: Do the MODE3 of LM98714 or LM98722 be used to the CIS(Mono color)?
Q4: Do you have a track record that corresponds with an external frequency divider circuit in order to lower this CIS clock frequency in the MODE1 of LM98714 or LM98722?
Q5：Are there any other imaging analog front-end devices that the CIS can use?
Please send me the informations.
Best Regards
H.masumoto
Hi all,
I use two LM98640 on the same board to digitize a 4-output CCD.
In a first step, I used the test patterns to validate my digital part inside FPGA.
All were fine and I checked the LVDS voltage which were good too.
In a second step, when I wanted to digitize the CCD video outputs, the behavior of the LM98640 changed:
- the LVDS voltages are not the same :
300mV low and 1.5V high (with 100Ohm terminaison resistor)
and only the low voltage changes when I change the "LVDS Amplitude and Common Mode Voltage" register
- the result of the conversion looks very noisy around a fixed mean value whatever we put on the OS- input video signal (fixed voltage from fonction generator) and whatever the values of the PGA and offset registers:
Mean value (decimal) ~10200 and the 10 LSB are flickering thus from ~9700 to 10700
Is this behavior is known ?
Is there something to do to check the health of the parts ?
Thanks a lot
vincent
Hi,
I am working with AFE 5809 and try it to configure it through FPGA. I am able to configure IC so that it sends custom patterns. I verified the custom patters using chipscope. But when I am trying to receive continuous echos through a AFE, it does not work properly. I am not able to figure it out what is going wrong while configuring AFE. The configuration data is attached. First 8 bits from MSB are address bits and remaining 16 bit are data bits.(Please visit the site to view this file)
Hi,
I'm working with the LM96551 Ultrasound Pulser in a novel industrial application. I am having some doubts / constraints about the viability of economically supplying power to this device (along with the other supplies required for my system).
Does anyone know if there exists an example schematic or app note showing a method for Generating and Sequencing the required voltages for the LM96551 device?
Thanks,
Stomp!
Hi,
I am working on a design with the AFE5809 and I see an odd behaviour regarding TX_SYNC_IN and the synchronisation word.
The FPGA interface with the AFE5809 is very similar to the one used on the TSW1200 evaluation board (see attached image from TI).
The AFE is configured initially with the demodulator off (the end system will be used with the demodulator on or off, so I am testing both operating modes) and a custom output word to configure the IDELAY for each channel independently. These are the register write operations to the ADC:
register 0x2 = 0x6000
register 0x5 = 0x156A
register 0x3 = 0x2000
register 0x4 = 0x0010
register 0x16 = 0x0001
The demodulator is then enabled with the following write operations to the demodulator:
register 0xDF = 0x8045
register 0xC2 = 0x6000
register 0xC5 = 0x55AA
register 0xC3 = 0x6800
register 0xC4 = 0x0010
register 0xCA = 0x1613
register 0xCB = 0x2772
register 0xE0 = 0x0001
register 0xE1 = 0x4000
register 0xCE = 0x0000
register 0xC0 = 0x0004
the FPGA interface is reset and synchronised again. The demodulator is then configured for normal operation with the following register write:
register 0xC2 = 0x0000
and the TX_SYNC_IN signal is generated with a frequency of about 15kHz.
The odd thing is that the behaviour of the first 4 channels is different from the last 4 channels. From the attached screenshots is possible to see a sync word (2772) at clock cycle 29 (yellow marker) on the last 4 channels, but not on the first 4. And there is a sync word on the first 4 channels at clock cycle 630 (white marker), but not on the last 4 channels.
The decimation factor is 5 and in fact for each channel there are: I sample, Q sample, 3 zeros. And when the sync word is present there are: sync word, I sample, Q sample, 3 zeros. I can see the correct sample pattern (sync, I, Q, zeroes) even at clock cycle 630 so it seems the demodulator sub-chip for channels 0-3 is really generating the sync word very late, but I don’t understand why and why the behaviour of the two demodulator sub-chips is different.
Best regards,
Matteo
What is the output of LM9833 and where to see it
is this IC pre programmed if not how to use this IC
Hi,
Am using ADS1298R in Continuous mode. I configured it for 500 SPS in High resolution mode. I get the 27 bytes data through SPI and from them I have split the Lead1 and Lead2 data. But when i plotted them in excel it looks like it has lot of noise but am sure that its ECG waveform. And when I recorded the data for 10 sec for 500SPS, i should get 5000 samples but am getting only 1500 samples. Can u help me in this issue?
Hi, all:
I tried to set the LM98620 to get a "more stable" & "low SNR" output. However, it's difficult to both achieve this goal ("more stable" & "low SNR") in my settings.
Maybe I put some wrong settings in LM98620 registers. But, where is the problem? I really have no ideas. Does anybody can help me analysis the output as shown below?
■OSX Inputs
OSR1(and other channels) and MCLK input
OSR1 According to light source(from weak to strong) react
So, I conjecture the OSX inputs are OK.
■Setting Imformations
OSX pixel rate: 20MHz(same as MCLK, SHP, SHD, TESTO1, TESTO0)
Input Mode: 6-channel(pixel rate MCLK)
Input Timing Mode: CDSb(CDS mode, sampled by SHP and SHD clocks)
Sample Timing Pulses routed to TESTO outputs(0x00[1]=1)
"SHP & AFEPHASE" routed to "TESTO1"
"SHD & !AFEPHASE" routed to "TESTO0"
LVDS ouput format: Mode 2a, 5 pair output(0x01[2:1]=01)
■LVDS Outputs Situation
Situation A: "more stable"(no sway), but "high SNR".
At AFEPHASE(0x02[3:2])=10, move SHP and SHD.
no light source
weak light source
strong light source
Situation B: "low SNR", but "less stable"(always sway).
At AFEPHASE(0x02[3:2])=10, move SHP and SHD.
no light source
weak light source
strong light source
If you want to know more information about settings, please tell me. Thank you :)
Hi,
I'm using LM96551/LM96530/AFE5803 to build a prototype. 8 channels of the LM96551 were parallel connected to excite a 2000pF ultrasound transducer. A picture below shows a received signal. A +50V and -50V pulser excite at the 1us. Then reflected shock lasts about 2us (from 1us to 3us). The amplifier seems not working in the range from the 3us to 8us. However, the received signal has a peak interference at 6us. The problem is that I cannot use the signal before 8us. Can anyone help me solve this problem?
I also capture the signal before and after the LM96530. Channel 1 is the signal after LM96530 and Channel 2 is the signal before LM96530.
Hello,
When a noise occurs in MDI interface, How much withstanding voltage does DP83848I have on MDI terminals?
Best Regards,
Toshiki
When the input to the AFE5801 is AC-coupled with a 0.1muF capacitor and the analog high-pass filter is enabled a ~10db gain is observed for 50kHz input frequencies as shown in figure 19 of the spec sheet.
The figure also shows that the gain can be removed by enabling the internal digital low pass filter.
Do I have to take into account this gain when designing an application? Is the effective maximum rating for 50kHz 10db lower than stated in the spec sheet or can I ignore this internal gain.
Thank you!
Hi,
I'm using AFE5803 evm for my school project.
I set up my evaluation board just as mentioned on page 3/4 of the 5803evm guide, but with the following two differences:
After powering up, the DC power says it overloads, then i cut off the power and find +5VA and GND of JP6 short-circuits.
In order to find out where the problem lies, I remove all the jumper caps and two ferrites (FB2/4), so the input power supply is completely kept apart with all the ICs, but the short-circuits still exists.
Does it means there must be some cracks or deformation inside the board between diffrent layers?
p.s.
another weird thing is, i find CLKBUF_VCC, the power supply of the clock synchronizer IC short-circuits with GND. and i find the VCO used with CDCM7005 on board conflicts with the one on the schematics (OSC1 on sheet 4 of the schematics) . It should be a 6-pin VCO but it's a 4-pin regular oscillator in fact. I'm very confused about that.
Hi,
I would like to ask you a question about the difference between AFE5807/5808/5808A/5809.
Sorry, I do not understand well the major difference between these devices but noise performance, digital-demodulator and power consumption.
Could you teach me what the major difference is?
Best Regards,
