Quantcast
Channel: Data converters forum - Recent Threads
Viewing all 5988 articles
Browse latest View live

AMC1035: Optimize Performance of the AMC1035

$
0
0

Part Number:AMC1035

Dear all,

I'll be using the AMC1035 in my newest design, where there are very high demands on the accuracy of the measurement. Since we measureme high AC voltages, high impedant resistor deviders will be used. There is an Application Note (SBAA214) for the AMC1304/05M25 on how to improve the performance (gain error and offset) in such a case. Is it required/possible to improve the performance of the AMC1035 the same way? Please note that I am only interested in the method 1 (without operational amplifier).


TSW14J56EVM: custom firmware and DSP blocks

$
0
0

Part Number:TSW14J56EVM

Hello,

I am using the TSW14J56 combined to the ADC12J1600 in an optical communication system. So far I have been using the functions provided by with the HSDC software and the ADC GUI, and everything seems to work properly.

Now I would need to move forward and I would need to understand the following:

1) Is it possible to communicate between PC and FPGA without the HSDC GUI with a standalone custom firmware?

2) Does the FPGA have DSP blocks that can be used, even if it comes as EVM?

Specifically I would like to perform the following operations:

1) In a first instance I would simply need to collect the digitised data with the FPGA and transfer them to the computer where I can post-process them, and I would like not to bother about opening the HSDC etc.

2) I would need to move some of the post-processing to the FPGA itself (namely some matrix-vector multiplication and some fft).

I am very new to FPGAs therefore any info would be very useful for me, including maybe beginners guide to the FPGA present in the TSW14J56EVM and any good begineers guide for FPGAs.

Kind Regards,

Francesco

  

DAC34H84EVM: TSW1400 DAC34H84

$
0
0

Part Number:DAC34H84EVM

After reading dozens of disparate (and desperate) requests for support on the TSW1400/DAC34H84 board combination I am still unable to get even the most rudimentary output from the DAC34H84 board. Since I intend to use the DACs at low frequencies I have installed pin compatible low frequency Mini-Circuits transformers on all channels.

I'm assuming the use of the internal clock (DAC JP5 pins 2-3 - any other changes to jumpers required?) to perhaps generate a 1Mhz DAC output square, sine, ramp ... wave output - anything to get a basic output to confirm the board set is working (just in case it matters I have AFE5809 EVM attached to the TSW1400 which IS working fine).

Can you provide me with a step by step example (perhaps with associated files) to make a very rudimentary confirmation that the board set is working (even just one channel)?

It seems unclear where some of the DAC34H84 config file examples reside (as opposed to DAC3484 examples). 

I'm never quite sure when the DAC3484 is referenced what pertains and what does NOT pertain to the DAC34H84.

As far as the explanation of the DAC3484/DAC34H84 GUI it seems I am unable to find a complete reference that explains the various settings in a single document.

ADS1232: Settling time stays at 400 ms even when A0 and TEMP is grounded???

$
0
0

Part Number:ADS1232

Hi, 

I am having trouble with the ADS1232 chip and nothing makes sense now. 

In my setup I have measuring a load cell with channel 1 input and and have channel 2 grounded. Also A0 and TEMP pins are grounded. My setup is actually very much like the application circuit in the datasheet on page 25 (figure 42). My setup does not have a external crystal either. 

I am using the PDWN pin for energy saving and battery longevity. Every time I need data I am powering up chip with PDWN set to HIGH, and when I get 1 sample I am powering the chip down with PDWN set to LOW. 

The problem I have is speed. The datasheet says there needs to be a settling time of 401 ms after toggling A0, or TEMP. I have both of these grounded and it STILL takes 401 ms for the DRDY pin to go low (sign of new data from page 19). So I ask you all this... What the hell is going on??? 

Please excuse my frustration... 

Thanks in advance. 

ADS1115: Is it possible that to avoid not losing configuration on power loss?

$
0
0

Part Number:ADS1115

This and other I2C chip I have test previously both reset to defaults each time they lose power.

I would like to use it standalone so I need to do not lose configuration values never (unless if it is configured again), is it possible?

Thanks

ADS8910B: Gain Drift Spec

$
0
0

Part Number:ADS8910B

Hello Team,

ADS8910B gain drift typical value is +/-2.5ppm/C. May I know if we should use the standard deviation (sigma) to estimate gain drift maximum spec?

For instance, +/-5 sigma (1 out of ~1.7M) max gain drift spec indicates +/- 12.5ppm/C.

Thank you.

Regards,

Ting

The software of ADS1299EEGFE-PDK Kit

$
0
0

HI,

    I bought  a ADS1299EEGFE-PDK Kit  several years ago.But I don't have the software now.

   Also it is unavaiable on the TI website.  I can't download it . 

   Can you help me ?

   Regards,

  Zhengbo Qu

ADS4122: Recommended driver

$
0
0

Part Number:ADS4122

Hello,

Our customer consider to use THS4551 and ADS4122 combination.

Here is concern that is ABS input voltage range of ADS4122's INP, INM pin which is AVDD + 0.3V = 1.8 + 0.3V = 2.1V.

And THS4551's positive output voltage range is  (Vs+) 3.0 - 0.2V = 2.8V.

Should we should add voltage clamper to ASD4522 input pin?

Or is there any system level suggestion or reference design?

 

Regards,

Mochizuki


ADS1278: data read wrong in Frame-sync

$
0
0

Part Number:ADS1278

Hi,

There is something wrong in reading data from ads1278 in Frame-sync mode.

Firstly, the configures are listed as table 1. And scope of SCLK,  FSYNC, DOUT1, DATA_IN is pictured as figure 1.

FORMAT[2:0]011
MODE[1:0]00
PWDN[8:1]00000001
FCLK25M
CLK6.25M
Vref2.5V

          tabel 1

figure 1

The problem is that when DATA_IN is +2.5V, the date that i read is 0x031000, not like the datasheet is 0x7fffff; And DATA_IN is -0.5V, the date that i read is 0x327100. So in this situation i can't identify the positive or negative of the DATA_IN voltage. And the data that i read is very steady. 

In order to apply more information, the data of different DATA_IN is listed as table 2.

DATA_INdata
2.5V0x031000
2V0x348000
1.5V0x675000
1V0x9a6000
0.5V 0xcd3000
0V 0xff2000
-0.5V0x327100
-1V 0x65a000
-2V 0xca6000
-2.5V 0xfca000

ADS122C04: Maximum value of offset drift at PGA disabled

$
0
0

Part Number:ADS122C04

Hi to everyone,

I just want to know whats the maximum value of offset drift if PGA is disabled ond the ADS122C04?


Thank you in advance!


Best regards,
Brian

ADS1675REF: ADS1675REF

$
0
0

Part Number:ADS1675REF

Hi guys,

As I am using the same hardware, I would like to have the FPGA code you are talking about. Can you please send me the code?

see you soon

Olonbayar

 

AFE4300EVM-PDK: Multiple sensing electrodes Matlab

$
0
0

Part Number:AFE4300EVM-PDK

Dear,

I would like to write the registers and read the output values in Matlab. I tried to make a Matlab program to write the registers with help of the Message Communication Protocol document.

After some attempts, I managed to write the registers according to the values in the device GUI (like I select the boxes in the GUI). I can also read back the register values and they are correct. For example: for changing the sample frequency to 860 sps in ADC_CONTROL_REGISTER1, I send 'w015170?' and then I send 'r01?' and I read back 5170 (also, the display of the AFE4300 EVM PDK board shows this value). However, I am not able to measure the potential difference over 1 pair of measurement electrodes (I keep receiving the 0A 0D default value) in Matlab.

When I adjust the registers in the GUI and try to read the measurements through Matlab, it does work. In my Matlab code, I first set all registers to the default values and then I adjust all the register values. Is there something else that I should add to my Matlab code, except all the register values?

Regards,
Jinke

ADS1298: ADS1298: can't read ID

$
0
0

Part Number:ADS1298

hi,

I have a problem with the SPI communication.

I can't describe the registers to configure the ADS1298 for my application. Therefore I tried to read only the ID at the beginning. But this gives me the wrong value back.

yellow : SCLK

green : MISO

blue :  CS

red : MOSI

my code:

ADC32RF45: Noise spurs resulting from use of DDC

$
0
0

Part Number:ADC32RF45

I am attempting to debug an issue we are seeing with an ADC32RF45 device. We have a custom board that has two ADC32RF45 devices on it giving us a total of four channels. We have manufactured multiple boards without issue. On one particular board, I am seeing a problem on one of the four channels.

Problem description:

Channel A of the second ADC is exhibiting noise spurs when running in DDC mode. I have a screen capture of the FFT spectrum from channel A below. The configuration for this test was:

990MHz DDC center frequency

3GHz ADC sample clock

Decimate by 4, so 750MSPS output sample rate

Test tone at 990MHz

To determine whether the issue was related to the analogue input of the ADC, I configured the DDC of channel B to the same configuration as channel A above and then enabled the DDC mux so that the channel B DDC was operating on channel A data. I then captured the data from channel B. I have a screen capture of the FFT spectrum from channel B below:

As can be seen, the noise spurs are no longer present when I use the DDC in channel B to process the data from channel A.


To further verify this fact, I configured the ADC32RF45 into bypass mode (bypass DDC). In this mode, I am capturing raw ADC samples from the ADC32RF45. Both channel A and channel B operate normally and do not contain the spurs visible in the first screen capture. This confirms the following:

- the issue is not related to the channel A ADC input circuitry

- the issue is not related to the channel A ADC interleaving and offset correction

- the issue is not related to the channel A JESD204B interface

From this testing, it can be seen that the only difference between a normal FFT spectrum and the noisy FFT spectrum is the channel A DDC circuitry inside the ADC32RF45.

I am not sure how this is possible though.

I did more testing to try and understand the behaviour of why channel A DDC is introducing noise spurs.

1) I repeated the above testing at a 1000MHz DDC center frequency. The following screen capture of the FFT spectrum is with channel A DDC operating:

1000MHz DDC center frequency

3GHz ADC sample clock

Decimate by 4, so 750MSPS output sample rate

Test tone at 1000MHz

By enabling the DDC mux again, I used channel B DDC to process the same data and this is a screen capture of the FFT spectrum:

Again you can see that simply by using channel B DDC circuitry, the noise spurs are gone. It can also be seen that the location of the spurs changes depending on the DDC center frequency.

2) The noise spurs are not present if there is no input signal.

3) I tried testing with all four NCOs set to the same frequency and set to different frequencies. It didn't have an impact on the noise spurs.

I am completely stumped as to how only the channel A DDC circuitry could be introducing noise spurs.

a) Is there a specific input power pin of the ADC32RF45 ADC that powers only the channel A DDC circuitry?

b) Is it possible for the channel A NCO clock to be 'unstable' while the channel B NCO is operating as expected?

c) Is there any other possible explanation for why the channel A DDC could be introducing noise spurs while channel B DDC operates as expected?

Lastly, I don't believe this is a configuration issue because we have multiple other boards where channel A DDC operates normally.

I am hoping you will be able to provide some further insight!

Thank you.

DAC9881: Glitch Issues in DAC

$
0
0

Part Number:DAC9881

Hi

I am trying to reject glitches from a DAC. We want highest possible resolution (about 18 or 20 bit) in a bipolar output of +-10V.

If we select the DAC9881 some glicht will occur. I have looked at the: http://www.ti.com/tool/TIPD142

This will help according to the note - but still some glitch will occur. 

How can we make this work with +-10V output?

regards


DAC38J82EVM: Matching the JESD204B line rate between the DAC and FPGA

$
0
0

Part Number:DAC38J82EVM

HI,

We are using JESD204B IP core (XILINX).

Ip core : JESD204(7.2)

application : Data transfer from FPGA(virtex - 7 (VC709) ) to DAC(DAC38J84) through JESD204B protocol at line rate of 6.4 Gbps.


configuration done on FPGA side.

     We are using reference clock of 160 MHz.

     so our line rate will be = (reference clock * 40) = 160MHz * 40 = 6.4 Gbps.

     configuration of line rate and reference clock is made from JESD204 PHY configuration tab of JESD204(7.2) IP core.


using the DAC EVM gui for DAC38J84 to configure the JESD204B we have a onboard oscillator 122.88 MHz.

       The the jitter cleaner IC LMK04828 is used generate clock and provide the CLOCK and SYREF to DAC and FPGA.

      using onboard clock we are able to configure using the quik start tab and the line rate we can get closest to 6.4Gbps is 6.144Gbps.

      clock generated for FPGA is 153.6 MHz.


what we need is to match the line rate between FPGA and DAC. Is it possible to generate 160MHz clock from LMK04828 by using
the reference clock of 122.88 MHz?

formula used to find device clock = Vin(refrence clock) * N (Divider) * P (Prescalar) / divider value.

Example = Vin = 122.88 N=10 p=2 divider value = 16

device clock = 122.88 * 10 * 2 / 16
= 2457.6 / 16
= 153.6

Thanks and Regards
Suraj

TLV2556: Need specs verification

$
0
0

Part Number:TLV2556

hi,

I am trying to find a few information on the data sheet and I cannot for FPGA coding. I need some technical support to verify this data sheet.

Some information are really confusing in the data sheet

thanks

hari

DAC8832: What is the noise level of 0.1-10 Hz?

DAC081S101: Creating ADC-DAC voltage memory

$
0
0

Part Number:DAC081S101

Hi Team,

I have customer inquiry below:

The customer wants to use an 8 Bit ADC with SPI output to directly connect to an 8 BIT DAC with SPI input to form what will essentially be an infinite hold time S/H.  Will the SPI output of a DAC081 directly drive the SPI input of an ADS7866 or some equivalent PN ADC to DAC combination?"

Thanks!

Jonathan

ADS5294: Sampling time specification

$
0
0

Part Number:ADS5294

Hi,

If I set the sample rate to 40MHz, during how much time the sampling capacitors are charged? I am having trouble understanding the timing specification of the ADS5294

Thank you,

Maxime Puech 

Viewing all 5988 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>