I am working on a circuit board using LM98640 to interface an FPGA. The datasheet specifies digital supply voltage of 1.8V, but Electrical Characteristics table shows that VIH and VOH min is 2.0V and 1.8V, respectively. Based on the Electrical Characteristics table, the I/O voltage (digital) can't be 1.8V. I suspect it should be 3.3V, but I guess my question is: what FPGA I/Os (1.8V or 3.3V) should the LM98640 interface to?
Thanks in advance for any insight/clarification.
-Simon
Hi folks,
I'm working on a design with an AFE module where I'll be taking advantage of channel compression so that I'll have multiple channels multiplexed onto a single LVDS lane. I'll also be using the decimation feature such that the device will have several clock cycles of output between samples.
One sample from each channel will be sequentially output on the single LVDS lane followed by several clock cycles of zeros. Then, when the next sample is available, again, one word from each channel will be multiplexed onto the lane followed by zeros. This repeats until we're done sampling.
If I'm not mistaken, I believe the DCLK and FCLK continue to run between samples.
Looking at this from the FPGA side where I'll be deserializing the samples, is there a preferred way to associate a sample with a channel?
For example, do I simply count the number of frame cycles to identify what byte is associated with each channel, or is there some kind of reference signal that channel 1 is now being output?
Thanks for any advice,
Matt
Hi all,
Could you tell me the minimum input ADCCLK frequency of TLV990?
My customer plans to use this device at 4MHz.
Regards,
Toshi
Hello TI support,
This is Parisa. We bought the TX-SDK-V2 evaluation board for ultrasound transmitter in order to do some measurement. In this level we need to program the Opal Kelly EXM3001 FPGA Module. would you send me the relevant code to be used for programming FPGA in order to transmit data?
Regards,
Parisa
I have built the Ultrsound transmit solutions( refence to http://www.ti.com/tool/TX-SDK-V1Need I configure the Opal Kelly's FPGA to make the lm96570 of the TX_SDK_V1 firing signal?Or the GUI (TI Ultrasound Tools)of the TX_SDK_V1 could do this by itself?
Hi all,
Could you please share the data of following specifications?
1. About INL and DNL, will the linearity is changed by the value of the PGA?
2. About CDS full-scale input span, is it range of a video signal between GND and offset level like case 2?
3. Is there the timing chart and time value for CLCCD, BLKG, OBCLP and ADCCLK?
Regards,
Toshi
Dear Sir,
Do you have Ultrasound Analog Front End With 204B interface product?
Hi all,
According to the datasheet of AFE5816, FCLK is the same frequency with ADC_CLK.
However my customer reported that the FCLK is a half of ADC_CLK,
and 12bit length of the data to be output are accommodated in one cycle of the FCLK.
It seems that the ADC sampling rate is a half of ADC_CLK.
Is there any divider function for ADC_CLK input?
ADC_CLK:
FCLK:
Regards,
Toshi
Hi,
I'm having trouble configuring the AFE5809 decimation filter.
I'm using the following coefficients take from a previous post for say decimation by 8 filter
uint8 pu8_fircoeff_DEC8[8 * 14]={
0x0F,0xEF,0xFC,0x60,0x06,0xBF,0xF1,0x00,0x23,0xFF,0xC0,0x00,0xBF,0xFF,
0x0F,0x1B,0xF6,0xF0,0x11,0xBF,0xD9,0x00,0x5B,0xFF,0x50,0x01,0x7F,0xFD,
0x0D,0x8B,0xF3,0xE0,0x18,0x3F,0xCA,0x00,0x7B,0xFF,0x00,0x01,0xFF,0xFD,
0x0B,0x5F,0xF3,0x10,0x1A,0x7F,0xC5,0x00,0x87,0xFE,0xF0,0x02,0x3F,0xFC,
0x08,0xCF,0xF4,0x50,0x18,0xBF,0xC9,0x00,0x7B,0xFF,0x10,0x01,0xFF,0xFC,
0x06,0x13,0xF6,0xF0,0x13,0x7F,0xD4,0x00,0x63,0xFF,0x40,0x01,0x7F,0xFD,
0x03,0x6B,0xFA,0x70,0x0C,0x3F,0xE5,0x00,0x3F,0xFF,0x90,0x00,0xFF,0xFE,
0x01,0x0B,0xFE,0x30,0x04,0x3F,0xF7,0x00,0x17,0xFF,0xE0,0x00,0x7F,0xFF} ;
SLOS738E section 8.6.2.1.3 advises to first write to 0xC6[7:0] with base address, which I have assumed is 0x0000.
It then advises to write 112bits to SPI address 0xC7, MSB first, although its not clear how these bytes are to be written.
i.e. does one convert each 14 byte row to MSB bitstream and send as 112 bits with single address
MSB First LSB Last
e.g. row one is sent as 11000111 00001111 ...... 10000011 1111111
0xC7 0x0F 0xBF 0xFF
or does one have to pack the 112 bit bitstream into 7x16bit transfers each with separate address as per the SPI protocol description in Figure 83 of SLOS738E?
I have tried both approaches but I cannot seem to get anything sensible out of the decimator filter when testing either in coeff test mode or injecting sinewaves using the sine test mode. I can see the sinewave and mixer outputs if I bypass the filter, but one enabled ... nothing..
If I use the ADDRESS + 112bit SPI transfer, I note that 0xC6 increments after each transfer, which I assumed is the expected behaviour. However when I try to test either with test mode sine, or test mode coeff (impulse), the with the decimation filter enabled, the output is zero, regardless of test mode.
I can confirm that in all test cases I perform a '1' write to Register 0 bit 2 (SPI_DIG_EN=0) after performing the RAM writes to load RAM.
I'm at a loss as to what to try next.
Is it possible to readback RAM coeff data to verify it has been written properly ? How precisely would this be done ?
Thanks
Hello,
I am looking for a ultrasonography transduder compatible with LM96530/550/570 chips by TI.
In other words this transducer must be compatible with TX-SDK-V2 Ultrasound TX Evaluation Kit
My application requires just one channel instead of 8 channels of above devices. So I am looking for a medical ultraound (ceramic ,I suppose) transducer.
I have been informed that are available some sensors that have the shape of little parallelepid of about 5x15x16 mm. They shoud be ideal for my application but I cannot find any supplier on the WEB.
I found only circular transducers from some Chinese manufacturer that are not targeted for medical ultrasonograpy (even if simple as mine) applications.
Thak you for your help.
Best regards
Vincenzo
Hello,
I'm working with TX-SDK-V2/NOPB. At the experiment, unfortunately one of the 50 volt out put of the board got short circuit with ground( I was trying to see the output pulse by osiloscope probe, then the probe connected the ground to one of the output channel. I'm not sure if the board damaged or not. Sub voltage didn't go up after that because the constraint current. Can you guide me what should I do now? How can I understand if the board damaged? how can I fix it? Dp you know any places to fix it?
Thank you
Parisa
Hello TI,
I'm working on ultrasound evaluation board by part number of TX-SDK-V2. By the package there is a schematic of power module board but there is no lay out file. The schematic without layout is useless. Is it possible for TI to give me the layout for power module board to get replaced instead of using 11 power supplies.
Regards
Parisa
Hi,
I am using Contact image sensor in my application, I am using LM98722 AFE to interface CIS sensor, i need help in CCD timing generation in LM98722 for providing clock signals to my CIS sensor..
I need to give 4 MHz clock input and 3.6 KHz clock input to my CIS Sensor, how can this two clock frequencies can be generated from LM98722 AFE CCD timing generation.
Thanks in Advance....
Regards,
Gokuleswaran R
Design Engineer
Sir/Madam,
After I am giving the power supply of +1.8V to 1.8V pin in EVM board, I checked the voltage level in banana cable connector cable pin at TX-SDK-V2 EVM board. It showed +1.4V only. but as per datasheet of LM96570, the digital core voltage should be in the operating ratings between +1.71V to +1.89V. Will it (+1.4) affect the operation of lm96570 IC? also I am not getting the output.
Thanks,
Sir/Madam
After I am giving the power supply of +1.8V to 1.8V pin in EVM board, I checked the voltage level in banana cable connector pin at TX-SDK-V2 EVM board. It showed +1.4V only but as per datasheet of LM96570, the digital core voltage should be in the operating ratings between +1.71V to +1.89V. Will it (+1.4) affect the operation of lm96570 IC? also I am not getting the output.
Thanks,
Hello,
We recently purchased a TX-SDK-V2 evaluation board, which comes with a Supply Voltage Cable with Phoenix Connector and 12 labeled Banana Plugs. However, the Phoenix Connector on the cable we received is much larger than the one shown in the manual and it does not mate with the PCB connector (photos below).
Would it be possible to get a replacement cable?
Thank you!
