Part Number: DDC1128EVM

ear TI,

I developed a "Daughter" Interface board for DDC1128EVM  for receiving  very low DC signal signal from PCBs photodiode sensors.

I use coaxial cable with SMB connectors to receive the signals of the photodiodes from a distance of around 12 inches. The PCB interface was mounted on the DDC1128EVM, as seen in the attached photo. The results obtained with respect to SNR, etc. and the histograms observed for each sensor show a large dispersion in the repeatability of the sampled signal, i.e., the "bell" shape is far from optimal. (photos attached).

The + 5V Power Supply both digital and analog is very clean with very low ripple. My questions are:

(1) Is it convenient to redesign the PCB interface so that it does not overlap the PCB of the DDC1128EVM in order to avoid contamination (noise) from the digital section of the evaluation board?
(2) According to the experience of other IT clients using the same hardware, would there be any restriction in connecting the photodiodes without previous use of some trans-impedance amplifier?

HISTOGRAMs: Channel 02 and 01, no bell shape; 

no bell shape; no bell shape;   This should be a good example of Histogram....

Please, see table below with configuration parameters, and values.

(1) Only the channels 01, 02, 03, 04 were connected to photodiodes (Highlighted in green)

(2) 

Thanks in advance.

Regards,

            Mario Marcoccia

IDSI - http://www.imds.com
1291-B NW 65th Place
Ft. Lauderdale, FL 33309
USA

Part Number: ADS1298

Dears，

Can you kindly help share the peripheral Circuits/Factors Affecting the Input Impedance of ADS1298,Many tks!

Part Number: ADS1299

  hi,Right now I am working on a project using ADS1299 with sequential montage for data acquisition. I have some question:

  Schematic description:

Power supply:(AVSS -2.5V,AVDD 2.5V DVDD= 3.3V， LiBattery)

Register configuration table

On Board ADS ID:0x3eLOFF:0x04 0x00: 0, 0, 0, 0, 0, 0, 0, 0
ID:0x00 0x3e:0, 0, 1, 1, 1, 1, 1, 0
CONFIG1:0x01 0x96:1, 0, 0, 1, 0, 1, 1, 0
CONFIG2:0x02 0xc0:1, 1, 0, 0, 0, 0, 0, 0
CONFIG3:0x03 0xec:1, 1, 1, 0, 1, 1, 0, 0
LOFF:0x04 0x02:0, 0, 0, 0, 0, 0, 1, 0
CH1SET:0x05 0x68:0, 1, 1, 0, 1, 0, 0, 0
CH2SET:0x06 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH3SET:0x07 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH4SET:0x08 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH5SET:0x09 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH6SET:0x0a 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH7SET:0x0b 0xe8:1, 1, 1, 0, 1, 0, 0, 0
CH8SET:0x0c 0xe8:1, 1, 1, 0, 1, 0, 0, 0
BIAS_SENSP:0x0d 0xff:1, 1, 1, 1, 1, 1, 1, 1
BIAS_SENSN:0x0e 0xff:1, 1, 1, 1, 1, 1, 1, 1
LOFF_SENSP:0x0f 0x00:0, 0, 0, 0, 0, 0, 0, 0
LOFF_SENSN:0x10 0x00:0, 0, 0, 0, 0, 0, 0, 0
LOFF_FLIP:0x11 0x00:0, 0, 0, 0, 0, 0, 0, 0
LOFF_STATP:0x12 0x00:0, 0, 0, 0, 0, 0, 0, 0
LOFF_STATN:0x13 0x00:0, 0, 0, 0, 0, 0, 0, 0
GPIO:0x14 0x0f:0, 0, 0, 0, 1, 1, 1, 1
MISC1:0x15 0x00:0, 0, 0, 0, 0, 0, 0, 0
MISC2:0x16 0x00:0, 0, 0, 0, 0, 0, 0, 0
CONFIG4:0x17 0x00:0, 0, 0, 0, 0, 0, 0, 0

hardware configuration：Sequential  Montage （SRB2 connect to The earlobe electrode,BIAS connect to another earlobe electrode 1N--8N connect to Brain scalp electrode,1P--8P  float,no connection ,SRB1float,no connection ）

 wave:

wave:X : point    Y:  uV

I have some question: 

   I want to make sure that my hardware circuit design is correct and my software configuration is correct?

   Help me to check whether the hardware design of BIAS part is correct?

wave part :Why is the base drift so serious ? The valur are incorrect!

Could you please help me find out what the problem is? 

    thanks a lot!!

Part Number: TLA2024

Tool/software: Linux

TLA2024 AIN1 is connected to the NTC thermistor, we are using the TLA2024 12 bits value from Conversion Data Register .

I used below formula for converting the temperature in degree Celsius but i am not getting the exact temperature.

1/T = 1/T0 + 1/B * ln( ( adcMax / adcVal ) – 1 )

here T0 is the 25°C value in kelvin

B value is 3455 of the 10K ohms.

adcMax  4095 and  adcVal is 12bit Conversion Register data.

can you please check, am i using correct formula?

if it is not correct please suggest to me, which formula I need to use here?

Part Number: ADS1298RECGFE-PDK

Tool/software: Code Composer Studio

Hi,

This issue is regarding firmware, I have download latest firmware code from web, I have extracted the code from zip file and imported it as project in CCS.

without modifying any part of code, I tried to generate the build but couldn't as I was encountering build issues. pls see the attached screenshot and provide your input to generate the build successfully.

I have one more query to be answered, since C5507 DSP is obsolete not recommended for new designs I am planning to use C5517 (recommended by TI) my query is, what all changes should be made in the code so that I can directly port it for C5517 and use it?

If this is not the right forum to ask this question, let me know where should I post this query.

Thanks,

Veera

Part Number: DAC8562

Hi, Do we have any software code example to provide?

Part Number: ADC12DJ3200

Hello Team,

My custom is debugging ADC12DJ3200. He has the following question:

Do ramp test mode test according to the DEMO given by TI official website. The data are completely normal. Then, the customer changes ramp test mode to normal operation without modifying the parameters, the data is wrong. The input signal is a single frequency sine wave signal.

The output phenomenon is:

The 240bit data is divided into 20 channels and 12 bits per channel. The simulation results show that only four channels of them are sinusoidal waves.

What is the reason for this? Any suggestions? Thank you in advance.

Regards,

Amy

Part Number: DDC264EVM

Hello,

we would like to use the DDC264EVM for our prototpye with a direct connection from our MCU to the DDC264. We do not want to use the FPGA (or a PC). We just want a direct connection from our MCU to following signals of the DDC264

 1) RSTn

 2) DCLK

 3) CONV

 4) CLK_CFG

 5) DIN_CFG

 6) DOUT

 7) DVALID

It looks like all of these Signal are accessible on large pads on the PCB.

During normal operation 1) - 5) are driven by the FPGA. 

Now my question:

Is it possible to set the corresponding FPGA output into some kind of high resistance mode, so that above signals 1) -5) may be driven externally? Maybe the FPGA is already in a high resistance mode if USB is not connected?

Thanks in advance.

Part Number: AMC1303M2510

Hi  Experts:

My customer is using the AMC1303M2510 for the in-phase current measurement in the servo drives. However, the device usually entered the fail-safe mode like the captured picture below:

you can the data out is hang on "1" before clock for 256 cycles (10MHz) , however, in the fail-safe mode, the CLK will hang on "1" for 70uS , is that correct ?

The device is in the fail-safe mode when the system is normally working , this is not we want to see because It will be false to drive the motor.

I checked the condition to trigger this mode :

a) The missing on the AVDD   b) The VCM > Vcmv (3V,  5V-2V)

My questions are:

1)  We checked the waveform of the AVDD , Vin+,Vin- with respect to the GND1, there is a little switching noise but is not sufficient to trigger the safe-fail mode ,

is there any factor to trigger this mode except for the two ones I listed?

2) We tried the value of the input capacitor on the AVDD , Vin+,Vin- as the datasheet recommended , but it has no effect. How to calculate the input capacitor to eliminate the common/differential mode noise effectively ?  

yellow: Data output    green: CLK out   Blue: phase current (DC current)

Part Number: ADC104S051

Hi,

I successfully use ADC104S051 for a sensor board. I connect 2 Sensors to one SPI bus in paralell mode (just one CS is low at a time)

But it turned out, that when I use long cables (4m) between The ADC104S051 and my µC, it happens, that the SDO signals start to output data on the 4th clock of the SPI clock instead of the 5th. In that case the read data is corrupted. If I use shorter (1m) cables everything works fine.

For suppressing reflections on the SPI lines I added 56Ohm Resistors in the SCK, SDI and SDO lines close to the µC.

I already measured the signals with the oszilloscope and all signals look good so far.

The SPI is running at a frequency of 125kHz.

I set the SPI mode to work with the trailing rising edge of the clock signal.

Is there any explaination for this problem or any idea what I can check to find the problem?

Thank you very much.

Best regards

Johann

Part Number: ADC12DJ5200RF

Hello Team,

we are upgrading a working hardware based on the ADC12DJ3200 to the ADC12DJ5200.

Expectation is that from the HW/pinout/SW/FW perspective the two parts are 1:1.

Nevertheless the JESD link with FPGA, by powering up the board with the new ADC12DJ5200, is failing.

We probed the lanes, and from signal integrity they look good.

Nevertheless the sync pattern doesn’t persist continuously.

Unexpected signals are observed before and after short burst of the expected signal. See the attached for example.

(Please visit the site to view this file)

We hooked up a high speed scope and monitored the signals as we ran different test patterns (as described in the JTEST section of the datasheet). We tried running K28.5, D21.5, steady high, steady low and Clock patterns. In all cases we noticed that the desired pattern is always preceded and followed by other patterns which sometimes look like K28.5 and D21.5 and clock patterns. The datasheet mentions that once a test like the clock pattern is initiated, the ADC should continue to output that pattern indefinitely. The SPI communication to the chip seems to be working fine as we can read and write different registers including the chip ID register. The signal integrity of the JESD signal also looks quite good. We modified our power supply to the board to accommodate the higher power requirements of the 5200 but still no luck in sync’ing JESD. We have also tried playing with the pre-emphasis on the ADC but we don’t think it is lossy trace issue since the 3200 board works fine and the fact that the data coming out of the ADC is not what we expect. We have other JESD devices on the board and they are working fine. And of course all our 3200 boards work OK.

• Can you comment, what in the HW upgrade could have got wrong?
• Do we need to upgrade the FPGA FW to get the part properly running?

Thanks for the follow up,

SunSet

Part Number: DAC3482EVM

Hi Ti,

I have the problem about the DAC3482EVM output.

My project is using ADS4249EVM, TSW1400evm and DAC3482EVM.I give the 200kHz sine wave and 20MHz CLK to ADC4249EVM. And using HSDC Pro to download the firmware(TIDA-00069). and the DAC 3482EVM config file is.(Please visit the site to view this file)

And i can get the clear sinewave in the digital Oscillosocpe, but when I change the input sinewave to Squarewave or Rampwave, the output in the oscilloscope is not right.

can you tell me why?

Sifei

Part Number: ADS131M04EVM

Hello, I am trying to setup my ads131m04evm board and I have noticed some very weird behavior when reading its output values.

I am inputting the same fixed 1v dc signal to all 4 channels. I measured the voltage being seen at each adc input, and as expected the positive input sees 1v and the negative 0v. However, the output doesn't match up with this at all. Channels 0 and 2 read about the same wrong value, while 1 and 3 do the same but are reading significantly higher.

Channel 0: 1.3756v
Channel 1: 1.9219v
Channel 2: 1.3753v
Channel 3: 1.9228v

Using the gain calibration registers i was able to correct channels 0 and 2 to get the correct input value of 1v, as I saw that the gain was consistently off by a factor of .72 across multiple input values. I used the same method to calculate the gain correction register value for channels 1 and 3 and set it to .52, but this actually caused the output values to be increased. I am now seeing 2.58v on those channels. There isn't any zero error so I haven't tried changing the offset registers. 

Another oddity that I noticed is that with a gain of 1, I shouldn't be able to read any higher than +/-1.2v but channels 0 and 2 seem to read up to 1.48v.  Here are my register values, nothing seems out of line other than ID. The only registers I am currently writing to are the gain correction registers.

Value of Register 0: 2401
Value of Register 1: 050f
Value of Register 2: 0510
Value of Register 3: 0f0e
Value of Register 4: 0000
Value of Register 5: 0000
Value of Register 6: 0600
Value of Register 7: 0000
Value of Register 8: 0000
Value of Register 9: 0000
Value of Register a: 0000
Value of Register b: 0000
Value of Register c: 5ccc
Value of Register d: cc00
Value of Register e: 0000
Value of Register f: 0000
Value of Register 10: 0000
Value of Register 11: 42aa
Value of Register 12: ab00
Value of Register 13: 0000
Value of Register 14: 0000
Value of Register 15: 0000
Value of Register 16: 5ccc
Value of Register 17: cc00
Value of Register 18: 0000
Value of Register 19: 0000
Value of Register 1a: 0000
Value of Register 1b: 42aa
Value of Register 1c: ab00
Value of Register 3e: 0000

The last thing I should mention is that I have an early engineering prototype of this board. Is this a known issue with early boards that has since been fixed in the newer revisions that have been released? Any insight into this problem would be greatly appreciated, thanks in advance!

Part Number: ADC128D818

Hi Team,

In one of my project we are using ADC128D818. My supply voltage and reference voltage is 5VDC.

Condition:

We didn't give any input signal, Some time we observed 5VDC on all input signal (All inputs are in float)

Please let me know what will be the issue. Please find the Schematic below.

Thanks Ashok 

Part Number: ADS4225

Hi,

I am building a scope with the ADS 4225 and based on the fact that the max sampling rate is not 1GS/s but 125MS/s i was searching for a way to take full advantage of its' 550MHz BW.

One way to do that is to use undersampling (for repetitive signals). Given that the resolution of the ADC is 12bits i need an extremely low jitter clock source.

In order to do undersampling i have to accurately measure the frequency of the input signal and then generate a precise clock frequency that will sample the input signal in just the right time.

Example:

Input signal: 70MHz (2nd Nyquist zone)

I need a sampling frequency of 1/70MHZ + 1/100 of the 70MHz period which is : 14.285nS + (14.285/100) = 14.42785nS = 69.31MHz in order to take 100 samples across 100 adjacent periods.

In order to generate that frequency i need to have a low jitter clock and then a pll which will programatically generate the sampling frequency that i need and eventually drive the ADC with that frequency.

I have chosen the clock LMK61E2 and considering the pll LMX2571.

Questions:

Is my undersampling approach correct as far as the sampling frequency is concerned?

How much will the pll output be affected jitter-noise-wise?

Any other suggestions?

Thanks in advance

Manos Tsachalidis

Part Number: ADS1232

Hi All,

I am looking into the use of the ADS1232 or something similar for a Resistive Bridge Measurement. The sensor i am using has a resistance range of 3 ohms (normal unstretched configuration) to 22 ohms (fully stretched). I will be using a microcontroller to interface with the analog-to-digital converter. I also have a supply voltage of 3.3V or 5V. So a unipolar supply is preferred. Some initial experiments show better results with constant current excitation, and i can see that some of the TI chips support this as a built-in feature. I am able to communicate via most methods (SPI, UART etc) so i don't have a preference. I have also looked at the ADS1220, ADS122U04 and others. 

I am new to resistive bridge measurements so would greatly appreciate some advice on the pros and cons of this ADC over others in your range. Higher resolution is preferred as the ultimate goal of this sensor is to characterize it for position measurements. 

Thanks for your time.

Kind Regards,

Zoran

Part Number: ADS1232

Hi ,

Currenty I am working on ADS1232 , I am facing issue with power down reset , whenever I  restart system  I have tried both options to control pwdwn pin  with rc circuit 1k and 100nf capacitor , and GPIO as well. Initially  PWD pin pull down with 470 ohm resistor and pull up it through microcontroller  100ms , but still same issue ,  I connect 12 loadcell and 12 ADC1232 and control though raspberry using SPI but some ADS1232's are giving unknown similar  values  0.137 like , I think reset problem , I want to finish project as soon as possible , also in production process , kindly give solution as soon possible

Thanks and regards

Paras Dayal

Part Number: ADS125H02EVM

Hello E2E forum members,

I'm having trouble getting the EVM to do anything that I think it should. It IS producing data. I'm trying to configure it to produce 40,000 sps sinc 5 filtered data. It is running on its internal clock. So that is 7.378 MHz +/- a couple percent Not 10.24MHz.  I THINK it should produce 28.8 sps when configured for 40Ksps at a clock freq of 7.37MHz. The MODE0 register is set to 0x83. This should satisfy the 10000 - 11111: 40 kSPS (fCLK = 10.24 MHz) . It is producing DRDY- at a 35.5Hz rate. The setting of 3 in bits 2:0 seems to select sinc4. No setting for sinc5. But maybe 40,000 setings produce sinc5 filtered data.

We want the sinc5 data with the first notch at the OWR of the filter. With an external clock of 2.048MHz we expect (and are told by TI) that this is a valid configuration.

Can anyone help?

Thanks

Terry Johnson

Consulting Engineer

Part Number: DAC38J84EVM

Hello everyone,

I'm using ZCU102 and DAC38J84EVM board. 

1. Program DAC38J84    (no alarm in DAC GUI)   (I'm using lane 0-3)

2. Program FPGA      (no alarm in DAC GUI)

3. Reset DAC JESD Core    (FIFO read empty alarms shown on received lanes)

4. Trigger SYSREF      (no alarm, SYNC asserted, FPGA JESD Tx starts transmitting data, but no DAC output, always 670 mV current)

Questions:

a. I think it's weird, if the FIFO is empty means no K characters received at DAC, then how can it get SYNC asserted. Or is that normal to get FIFO empty alarm before CDS. 

b. If FIFO read empty happens, what might be the cause, and how to debug it

c. I can pass the NCO test alone(hardware level should be fine), but still can not get any output with the (see capture below) FPGA JESD Tx Core, seems it pass the CDS, LAS and starting transmitting. What might cause this?

Regards,

Yawen

Part Number: ADS124S06

Hi,

I am currently working on a code to collect data from one ADS124S06 to an Arduino Uno. I have run a problem/question: Is the DRDY pin necessary (ie can it be tied LOW or HIGH) when using the RDATA command to collect data?

Thanks,

Spencer