Part Number: DAC8811
Hi all,
I have a question about the update timing of DAC output.
The below section of DAC8811 datasheet described that when CS sets to high the new data from the serial register is loaded to DAC register.
However, the section of 8.5.1 DAC8811 Input Shift Register described that the DAC output is updated on 16th rising edge of SCLK as below;
Which is the correct behavior?
Regards,
Toshi