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ADS42JB69: Driving the SYNC~ pin with LVDS from Arria 10 FPGA

August 28, 2019, 9:24 am
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Part Number: ADS42JB69

Hi, 

Our company is using ADS42JB69 to send data to FPGA.

I have read from the other post that we should use LVDS to drive SYNC~ and SYSREF pin for JESD204B on ADS42JB69.

However, from the Arria 10 FPGA (and the LMK04828) datasheet, the LVDS has a common voltage of 1.25V, with 1.125min and 1.375max.

But the datasheet of ADS42JB69 states that the input common mode voltage should be 0.9V. 

So I don't understand how this gonna work since we have this voltage difference and it's DC coupled.

Thank you so much!

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TSW1400EVM: DAC32H84EVM

August 28, 2019, 1:09 pm
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Part Number: TSW1400EVM

I try use TSW1400EVM + DAC32H84EVM, but it only support 2 channel, are there available firmware support 4 channel ?

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Compiler/ADS1146EVM: ADS1146

August 28, 2019, 2:25 pm
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Part Number: ADS1146EVM

Tool/software: TI C/C++ Compiler

Hello everyone 

I was working with the ADS1146 and I read information from the datasheet... I read Verp and Vrefn are external sources so Could any body help me with a diagram of the ADS1146? I mean how should i wire it?

Iam working on Arduino Board... and i've never used an ADS1146...

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ADC16DX370: Questions about JESD Link Behavior

August 28, 2019, 2:32 pm
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Part Number: ADC16DX370

Dear Supporters,

Our application is a custom integration of FMC144 with Arria A10 SoC Development Kit. There is no reference design.

We have implemented a rudimentary JESD receiver communicating with the pair of ADC16DX370s.

The 2 ADC16DX370 chips on FMC144 are configured with the default register settings. CLKIN is generated by LMK04828 at 148.5MHz.

In this bring-up test configuration, FMC144 input A2 (VINA on the 2nd ADC16DX370) is driven by a 3.3V CMOS square wave at 14.85MHz.

This SignalTap capture shows the expected behavior immediately following completion of the ILAS:

However, even though SYNCb remains high, ADC16DX370 behaves as though the link has broken around sample 930, repeatedly sending BCBC followed by foreshortened ILAS:

The link eventually is re-established, for example after sample 7936:

Unfortunately, the link breaks intermittently thereafter. Here is the final example from this SignalTap capture (after which the link remains stable for more than 2000 samples, to the end of the capture):

My questions about this behavior are

Q1: Why would ADC16DX370 behave as though the link has broken under these circumstances?

Q2: Will the link remain stable after some point, so long as SYNCb remains unasserted by the receiver?

I have further questions about the assertion of the datak bit, which identifies a byte as a control character.

This capture highlights the character FC sent during ILAS is correctly identified as a data byte:

However, this capture highlights bytes received by the FPGA which should be data bytes but for which datak happens to be asserted:

Q3: Is this the expected behavior of the datak bit?

Q4: Can the JESD receiver safely ignore the datak bit?

Hopeful thanks in advance for your answers --todd

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ADS7263: Recommended Electrical Connection for ADS7263S Thermal Pad

August 28, 2019, 3:34 pm
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Part Number: ADS7263

The ADS7263S converter comes with a Thermal pad under the part that does not appear to have a defined electrical connection. My preference would be to connect this to my board ground planes. Please let me know if there is any reason not to connect the thermal pad to ground.

Thank you,

Randy Holmberg

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ADS127L01: SPI Writing to Read-only Registers Safe?

August 28, 2019, 4:16 pm
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Part Number: ADS127L01

I plan on accessing the internal registers in multiple ADS127L01 devices over SPI. I'd write calibration data to specific registers (CONFIG, OFC, FSC), then read all registers back. It would be a convenience for my circuit to simply write and read all the same eight registers in the same sequence (WREG= 0x40, 0x07, RREG = 0x20, 0x07). I know that two of the registers, the first and last in address order (ID, MODE), are designated as read-only, but I haven't found a definition of "read-only" in the data sheet. What I'd like to know is whether my excess writes to these two registers (with placeholder data =0) will be harmlessly ignored while the other six registers are properly updated?

Separately confirming: in this scenario, both commands each require a single CSN assertion about 80 SCLK cycles wide, and the first register bit read on DOUT would be sampled by my circuit on the 17th falling edge of SCLK, where I'd begin pumping 64 zero bits into DIN.

Thanks.

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[FAQ] What are the main differences between the ADS1281, ADS1282, ADS1283, and ADS1284 products?

August 28, 2019, 8:23 pm
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Can you help explain the differences between these devices?

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ADS122C04: Inconsistencies in the datasheet

August 29, 2019, 12:17 am
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Part Number: ADS122C04

Hi,

In Table 27 on page 56 of the datasheet, description and setting of Register 02h (described on page 44) mismatch :

With 55h it should be : Conversion counter enabled (DCNT=1), Inverted data output enabled (CRC[1:0] = 01b) , burnout current sources disabled (BCS=0) , IDAC = 500 µA (IDAC[2:0] = 101b)

You can find the same type of error in Table 29 page 60 :

With 98h it should be : Conversion counter disbaled (DCNT=0), Inverted data output enabled (CRC[1:0] = 01b), burnout current sources enabled (BCS=1), IDACs off (IDAC[2:0] = 000b)

Regards,

GB.

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ADS1292ECG-FE: Access to evaluation PC source code

August 29, 2019, 12:44 am
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Part Number: ADS1292ECG-FE

Hi,

  I have been tasked with putting together a demonstration utilizing the ADS1292ECG-FE platform.  I can access the MSP430 firmware source code in the TI installation directory, but I cannot find anything concerning the supplied PC application (ADS1x9x ECG-FE).

Is it possible to get access to the PC source code for the ADS1x9x ECG-FE program so I can speed up my development by seeing how your demonstration kit handles the PC side (especially the USB comms)  ?

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ADS4449: ADS4449: SPI logic level

August 29, 2019, 1:23 am
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Part Number: ADS4449

H i team,

The ADS4449 datasheet describes "All digital inputs support 1.8-V logic levels. SPI supports 3.3-V logic levels". It means that SPI supports 1.8V logic level and 3.3V logic level. But the typical value of High-level Output voltage of SDOUT is DRVDD (1.8V). When ADS4449 communicates with 3.3V chip in SPI, does SDOUT signal line need additional circuit to convert to 3.3V? In other words, can the 3.3V chip recognize the SDOUT high-level of ADS4449?

Best Regards,
Amy

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CCS/ADS114S08: spi communication

August 29, 2019, 1:42 am
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Part Number: ADS114S08

Tool/software: Code Composer Studio

I am using ADS114S08, this converter is conneted to DSP28335, but when I ues SPI to send a RREG command to ADS114S08, the return value is always 0x00（the value should be 0x80, I also use RREG command to read other registers of ADS114S08, the result is same

here is my code

spi configuration:

    SpiaRegs.SPICCR.bit.SPISWRESET = 0;    

    SpiaRegs.SPICTL.bit.CLK_PHASE = 1;   //CPHA = 1
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 0;
    SpiaRegs.SPICTL.bit.TALK = 1;

    SpiaRegs.SPIBRR =0x0004;
    SpiaRegs.SPISTS.all=0x0000;        

    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // CPOL = 0
    SpiaRegs.SPICCR.bit.SPILBK = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = 7;


    SpiaRegs.SPIPRI.bit.FREE = 1;
    SpiaRegs.SPICCR.bit.SPISWRESET  = 1;

   void main(void)
{
    InitSysCtrl();
    InitSpiaGpio();
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();

    //spi_fifo_init();         // Initialize the Spi FIFO
    spi_init();              // init SPI

    adres_H = 0;
    adres_L = 0;
    adres = 0;
    rdata = 0;
    sdata = 0;

    CS_L;
    DELAY_US(1);

    rdata = spi_8bit(0x2000); // reset command
   
    DELAY_US(2000); // 4096*tclk
    CS_H;
    DELAY_US(1);
 
    CS_L;
    DELAY_US(1);
    rdata = spi_8bit(0x2100);
    DELAY_US(1);
    rdata = spi_8bit(0x0000);
    DELAY_US(1);
    rdata = spi_8bit(0x0000);
    DELAY_US(1);
    CS_H;

   Uint16 spi_8bit(Uint16 a)
   {
     Uint16 data;
     SpiaRegs.SPITXBUF=a;
  
     while(SpiaRegs.SPISTS.bit.INT_FLAG != 1)
     {
     
     }
     data = SpiaRegs.SPIRXBUF;
     return data;
   }

  

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ADS1271: Behavior above specs.

August 29, 2019, 4:55 pm
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Part Number: ADS1271

I have an application using the ADS1271 ADC, the inputs come in a true differential form.

Occasionally the values might exceed the analog limits, the ADS1271 has a 5V power on AVDD and a reference at 2.5V. The inputs will some times deviate up to +/-3V giving a 6 volt differential for a very short time.

I expected the ADC to clip the values at 7FFFFFh and 800000h, but it is not.

Is this to be expected because of the signals going out of specs briefly?

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TSW1400EVM: "No firmware. Please select a device to load firmware into the board" HSDCv5.0 with AWR1642+mmWave DevPack

August 29, 2019, 8:37 pm
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Part Number: TSW1400EVM

Hi

I am using TSW1400EVM with AWR1642BOOST and mmWave DevPack. I am using HSDC Pro v5.00 with DFP version 00.07.00.04 and 00.09.01.06 (experimented with both, but the same error still occurred) on a Windows 10 laptop. 

I would like to capture raw data via the TSW1400 but HSDC pro constantly shows “No firmware. Please select a device to load firmware into the board” after I select AWR16xx_lvds_4Channel_ddr_4bit_par_centre_16_bit, or any others such as ADS5294_1W_12b as suggested in another thread.

I followed the setup instructions as given in the “mmWave Sensor Raw Data Capture Using the TSW1400 Board” training video, and installed the relevant applications.

I understand that this error usually arises from not enough current supplied for the board to draw from, but the board is connected to a 5V/5A output of a DC power supply. I have also tried using 5.4V instead as it worked for another guy from the other thread, but the error still remains the same.

I have noticed the board draws about 0.38A to 0.39A when the board is first started up, and around 0.59A when attempting to load the firmware. 

My setup is as follows:

 

I would like to know any troubleshooting methods available or if any of the jumpers are in the wrong positions. Thanks in advance!

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CCS/ADS1274: SPS and Discrete mode

August 29, 2019, 9:51 pm
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Part Number: ADS1274

Tool/software: Code Composer Studio

According to the data sheet, maximum data rate is 144kSPS @ high-speed mode(fclk=37MHz).

Does it mean 144kSPS/channel or total 144kSPS(36kSPS/channel)? 

What is the maximum sampling if I use all 4 channels?

How do I use discrete mode?

Is there any example to reference? (MCU, HW wiring, Code, etc.)

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DAC8728: Can Vref be changed while the DAC is active?

August 29, 2019, 9:59 pm
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Part Number: DAC8728

Hi data converters team!

I'm posting this on behalf of my customer. This is for a test/measurement application.

Can the vref value be changed while the DAC is enabled and active?

Thanks,

Lauren

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ADC3421: Time between CLK-in to valid data out

August 29, 2019, 10:32 pm
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Part Number: ADC3421

In our application we programm the ADC via SPI before the CLKin is applied. The CLKin can only be applied for a certain time until the acqusition is done.

Once the CLKin is applied it will take some time until the PLL for DCLK/FCLK is locked - this is typically ~500us (as we measured until a stable FCLK output is present). 

But it needs much more time until valid output-data are available - even if testpattern (ramp or sine) are generated internally, it takes a longer time until the testpattern data are coming at the output.

I can't say how long it takes, but after ~2 seconds the output data are stable - but this is too much for our application.

I did not find any number in the datasheet for the delay between first CLKin edge and valid-data output.

Can you please let us know if the above described behaviour is expected and what the minimum time delay between CLKin and valid-data output is ?

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DAC7571: Some quesitons

August 29, 2019, 11:20 pm
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Part Number: DAC7571

Hi Sirs,

Sorry to bother you.

1. VDD is 5V_STBY, and I2C signal pull up to 3V3 Run, as shown in the figure, please help to confirm whether this behavior is correct? Or I2C also pull up to 3V3_STBY is more suitable?

 

2. As shown schematics, for example U7, we get DAC address as 0x98, but when the power is turned on, but it detects three addresses as 0x3E/0x6C/0x6E. By the way, we use 100KHz standard I2C, please help to confirm.

 

3. Above three addresses 0x3E/0x6C/0x6E, when we command these three addresses, only 0x6C is successfully written, but DAC output has not response.

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ADS8568: Need Simultaneous 32 Sensor real time data using ADS8568 - All reading must be simultaneous

August 29, 2019, 11:24 pm
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Part Number: ADS8568

Hi TI Team,

I am working on the redesign of the existing Sensor based system and this is the first phase for me and our company.

Specifications/system configuration in existing hardware is as below:

- It has four ADS8568 ADCs to take the data simultaneously of all 32 channels (4x8 channels) and must receive data at same time for all 32 channels. (Currently receiving data simultaneously within the 8 Channel ADC but could not get sync with all external ADC Channels) (Image as per below) )

- Using four different SPI (each ADC have a separate SPI) connected with Processor(i.MX6)

- Four CONVST signal(each ADC have a single CONVST connected with processor and within ADC all the CONVST_A,B,C,D is shorted)

- input support 0 to +/-45V and using resister divider with AFE to limit to +/- 12V

- Set the reference voltage internal to 3V and +/-4VREF to support +/-12V input

- Using SW (Software) method support in ADS8568

To redesign the existing system, I need to debug the existing system to achieve the synchronization between all the 32 channel and must receive data simultaneously especially with external all four ADCs.

So, I need TI expert help to achieve this goal and to successfully redesign the new hardware,

1. Will I need to common all four CONVST signals connected with the four ADCs?

2. Is that HW or SW configuration will give the better results or low latency?

3. Daisy chain will help here or will receive more latency than seperate SPI?

4. Is that I need to give External common Clock at XCLK to all the ADCs?(Existing system is using internal clock only)

5. Is that I need External VREF which will be common to all four ADCs? Is that effect the synchronization?

6. Will I need to Monitor/use BUSY/INT signal connect with processor to take readings/conversation in sync for the next sequence of data?

7. Will it Parallel mode(Digital IOs) is better or Serial mode(SPI) to get the data simultaneous using processor?

8. Is that Processor based design will work or need to select FPGA or CPLD for the new design based on your expertise for the ADC data sync?

Let me know if you need more details regarding existing system.

Thank you,

Nilav Choksi

 

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ADS124S08: When AVDD short with GND , what could be the DRDY signal level

August 29, 2019, 11:38 pm
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Part Number: ADS124S08

When AVDD short small duration and recover back the AVDD. The 1st set of data from ADC is wrong (8388608) which expected data is 16612216 decimal value. When we get the 2nd data from ADC are OK.

Script comment observation: 

1. Can we short the AVDD signal short time ??

2. Why the DRDY pin is toggling continuously after AVDD short ?

3. How we can resolve this issue by Hardware or Software ??

Application software observation 

1. When short the +5VDC the application get stopped completely and not toggling for any control signal of the ADC.

Regards,

Arumugam

 

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ADS1263: Shut resistor recommendation

August 29, 2019, 11:57 pm
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Part Number: ADS1263

Hello,

Can you please recommend an optimize shunt resistor to sense current?

Is there any technical document describng how to select shurt resistor values?

This is simple structure of the system:

PMIC(ex. 1.1V supply) ------(ADS1263 input P) Shunt resistor 10mohm (ADS1263 input N)-------device for current measuring

 Here is ADS1263 design parameters:

1. AVDD : 5V

2. DVDD : 3.3V

3 Ref Voltage : internal 2.5V

4. PMIC supply range : 0.5V~3.3V

5. current range : 0mA ~ 500mA

Thanks!

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