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LM9833: EVK

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Part Number: LM9833

Hi Sir 

May I know LM9833 have any design guide and EVM user guide ?

We would like to apply a EVM to verify our application

Thanks 


AFE5816: what`s the delay between inter processor with lvds ouput pin ?

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Part Number: AFE5816

dear sir

     l want to use afe5816 in my detection device. l want to know the delay time between the inter digital processor with lvds output pin ?

AFE4900: AFE4900 user manual, Winxt oscilloscope software, driver software, firmware code

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Part Number: AFE4900

Hi Ti team:

Customer Xunlong purchased an AFE4900 Demoboard through our ,order number PO: 11003637297.

Where can we download the relevant information such as  user manual, Winxt oscilloscope software, driver software, firmware code?

Thanks

CQ.LV

DAC7311: Output high frequency harmonic problem

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Part Number: DAC7311

Hi Team,

DAC7311 is used for RF signal, but the output has high frequency harmonic which has bad effect on RF performance.

DAC7311 is powered by a 3.3V LDO and the output is set to 0.9V, the frequency spectrum of power supply is as below, it can be seen that the power supply is very clear at high frequency.

However, the output frequency spectrum shown below has high frequency harmonic at about 311kHz/631kHz/941kHz/1.251MHz. The output is disconnected with the load and is measured directly. The SPI clock frequency is 4.5MHz, that why there is 4.5MHz harmonic in the picture.

Could you please tell why the output has high frequency harmonic? Thanks!

Best Regards!

Hao

ADS131A04: ADS131A04 Master Mode

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Part Number: ADS131A04

Hi, 

I will use the ADS131A04 on synchronous master mode. Previously i worked on it with the Asynchronous Interrupt Mode, so on every interrupiton of DRDY, the MCU send a null cmd to recieve a sample for every channel. 

So in master mode is there no need to send null commands to  the ADS131A04 for recieving data, or we have to send null commands for channels to recieve samples even in master mode. 

Best Regards. 

ADS1299EEGFE-PDK: Read ID register issue

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Part Number: ADS1299EEGFE-PDK

Hi Ti,

       I want to use ADS1299  with SPI. The coding background is linux.

       I test with my simple C code as below:

   

#define MAX_BUF 64
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
typedef unsigned char uint8_t;
static void pabort(const char *s)
{
        perror(s);
        abort();
}

int spi_init ()
{
  int ret=0;
  int lsb = 0;
  int mode = SPI_MODE_1;
  int speed = 500000;
  int bits = 8;
  int fd;

  //Open device
  fd = open("/dev/spidev0.0", O_RDWR);
  if (fd < 0)
    return -1;

  //SPI Mode
  ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
  if (ret == -1)
    return -1;

  ret = ioctl(fd, SPI_IOC_RD_MODE, &mode);
  if (ret == -1)
    return -1;

  //Bits per word
  ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
  if (ret == -1)
    return -1;
  ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
  if (ret == -1)
    return -1;

  //Max speed in Hz
  ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
  if (ret == -1)
    return -1;

  ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
  if (ret == -1)
    return -1;

  //MSB FIRST
  ret = ioctl(fd, SPI_IOC_WR_LSB_FIRST, &lsb);
  if (ret == -1)
    return -1;

  ret = ioctl(fd, SPI_IOC_RD_LSB_FIRST, &lsb);
  if (ret == -1)
    return -1;

  printf("spi mode: %d\n", mode);
  printf("bits per word: %d\n", bits);
  printf("lsb: %d\n", lsb);
  printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);

  return fd;
}


int main (int argc, char *argv[])
{
  int fd, opt, ret=0, res=0;
  uint8_t spiregister[2], rx[2];
  unsigned short int delay = 50;//10
  int i;

  memset (spiregister, 0, ARRAY_SIZE(spiregister));
  memset (rx, 0, ARRAY_SIZE(rx));

  struct spi_ioc_transfer tr =
    {
      .tx_buf = (unsigned long)spiregister,
      .rx_buf = (unsigned long)rx,
      .len = ARRAY_SIZE(spiregister),
      .delay_usecs = delay,
      .speed_hz = 500000,
      .bits_per_word = 8,
    };

  //Init_SPI
  fd = spi_init();

  if (fd == -1)
  {
    printf ("Error open spidev device\n");
    close (fd);
    return 1;
  }


    printf ("Send sdatac\n");
    spiregister[0] = 0x11;            //RREG 0x20
    ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
    if (ret < 1)
      pabort("Config : can't send spi message");
    usleep(2000);

    for (i = 0; i < ARRAY_SIZE(spiregister); i++)
      printf("tx%d = %02x\n", i, spiregister[i]);
    for (i = 0; i < ARRAY_SIZE(rx); i++)
      printf("rx%d = %02x\n", i, rx[i]);

  printf ("Send RREG\n");
  spiregister[0] = 0x20;            //RREG 0x20
  ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
  if (ret < 1)
    pabort("Config : can't send spi message");
  usleep(100);

  for (i = 0; i < ARRAY_SIZE(spiregister); i++)
    printf("tx%d = %02x\n", i, spiregister[i]);
  for (i = 0; i < ARRAY_SIZE(rx); i++)
    printf("rx%d = %02x\n", i, rx[i]);
  usleep(100);
  printf("rx%d = %02x\n", i, rx[0]);
  close(fd);
  return 0;
}

 and my output is 

I always get 0x3e(the ID) at the step of sdatac command, I dont know why, can you tell me what can I do to check out the possible problem?

VSP5610: in one channel not getting 3 count

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Part Number: VSP5610

Hi,

I have conifigured Afe in cds mode and i have ground my input signal.In 2 channels i am able to see 3 counts. while in other in one channel i am able to 150 counts why?

My AFE Configuration settings are

I have configured Mclk of 1 Mhz.

Clamp mode is pixel clamp

Reference and clamp level selection is internal Reference 2.2v.

channel polarity-CCD

And counts set in SHP AND SHD ARE

SHP_CH 1&2_Rising edge-6

SHP_CH 1&2_Falling Edge-14

SHD_CH1&2_Rising Edge-31

SHD_CH1&2_FALLING-38

SHP_CH 3&4_Rising edge-7

SHP_CH 3&4_Falling Edge-14

SHD_CH3&4_Rising Edge-32

SHD_CH3&4_FALLING-38

Gain=1

I have attached the schematic picture of Afe.

AFE5803: cap size

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Part Number: AFE5803

I have a couple of queries re. the AFE5803 that I’d appreciate guidance on.

 

  1. Are capacitance values 100nF (to INxP) and 15nF (to INxM) enough for low frequency (700kHz) operation?
  2. Does the hardware reset pin when active set digital output pin impedances high?

 


AMC1304M05-Q1: AMC1304

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Part Number: AMC1304M05-Q1

I will be measuring the inductor current in a dual interleaved boost converter and the inductor current of an inverter.

1) In the examples presented in datasheet of the AMC1304, its used to measure currents of a half bride topology or full bridge, will it work when measuring the inductor current of a boost converter?

2) For powering the AMC1304, I will be stepping down 80V to 12V using an isolated power supply (flyback converter) to power the 12V side of the AMC1304 and an isolated high side low side gate diver, this 12V then gets stepped down again using a non-isolated power supply to 3.3V for powering of a TMS320F28075 dsp and the 3.3V side of the AMC1304. In the datasheet of the AMC1304, a floating power supply is used to power its 12V side. Since I'll be using three AMC1304 for current measurement will my method of power supply work correctly, (80V to 12V isolated) (12V to 3.3V non isolated)?

DAC38RF83: DACCLKSE

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Part Number: DAC38RF83

Hi

What is the input DACCLKSE Electrical Characteristics? ( minimum\maximum voltage ... freq , )

AC \ DC coupled needed  ?

Shlomi

DAC161S997: Write command is invalid

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Part Number: DAC161S997

Dear team,

Below the first picture is the programming. One Write command, and three read command. And the CSB(blue), SDI(yellow), SDO(green), SCLK(pink) waveforms are as following. We can see that, the SDO still has no change. Could you please tel me the reason? The schematic is as below. In addition, about the timing requirement, in our datasheet the tZSDO(CSB falling edge to SDO valid) should be smaller than 35ns, but the cusomer's MCU can't meet this requirement. Is this fault related to the timing requirement?

Thanks & Best Regards,

Sherry

ADCPRO: any known bug with dBFS scaling with ADS1282EVM?

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Part Number: ADCPRO

Hello,

I've been gathering some data using ADCpro and a ADS1282EVM board.

I also process data with matLab to ease comparing spectra. I think I'm finding some lack of coherence. The two spectra below are supposed to be from the same data :

To scale according to dBFS I just divided all data by « Max Code » included in the data text file generated by ADCPro.

I’ve tried a few different PSD (power spectral density) calculation techniques in MatLab and the dBFS noise floor is always at the same place, like 30dB lower than what is indicated by ADCPro.

Reading older posts related to this kind of problems I found :

https://e2e.ti.com/support/data-converters/f/73/p/258714/904881?tisearch=e2e-sitesearch&keymatch=ads1282evm%25252520adcpro%25252520dbfs#904881

and

https://e2e.ti.com/support/data-converters/f/73/t/94449?tisearch=e2e-sitesearch&keymatch=%2520user%253A65187

The problem those users found could be the same I see.

In both cases there seems to be a possible bug in Y-scaling recognized from TI side, but in both cases the thread ends without a clear solution or work-around (as far as I can understand). Both are quite old.

Do you have updates on these topics ?

Would it be possible to have a detailed description on how dBFS values are calculated ?

ADS124S08: Range of REFN0 and REFP0 ...and resulting digital code?

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Part Number: ADS124S08

Hi all,


I'm reading the datasheet for this part and I'm confused about the range of REFN0 and REFP0. My experience is with single ended ADCs not differential types/signals. Does REFN0 ever needs -2.5v to convert a true bipolar input signal that swings between +2.5v and -2.5v? Let's leave the gain out of this for now, I understand that the gain reduces the input range by VREF/Gain. Could you also elaborate on how the 24 bits range gets "distributed" over the differential input range (-2.5v to +2.5v) please?

Thanks.

DAC128S085: What are the MSPS of DAC128S085

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Part Number: DAC128S085

1.What are the MSPS of DAC128S085

2.What's the difference between A and B, other than the number of channels.Is the protocol the same?

ADS8556: Configuration in software mode.

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Part Number: ADS8556

I am trying to get the ADC working in software mode after a successful attempt in the hardware mode. As the datasheet mentions that initially the configuration register by default has the value 0X000003FF, I didn't write anything to the register and only toggled the Conversion start of channel pair A high. But the BUSY pin didn't go high like its supposed to when conversion start goes high. Kindly help me to get the ADC to work in software mode.


ADS54J69: JESD204B resynchronization

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Part Number: ADS54J69

Hello,

My customer has a question about ADS54J69.

[Q]

They are evaluating ADS54J69 with Xilinx Kintex7 JESD204B v7.1 Logic Core IP.

Normally JESD204B is linked up normally.

However, sometimes JESD links are intermittently interrupted and it is resynchronize.

In this case, the following errors have been observed :

* RX disparity error from JESD204 PHY

* RX Not In Table from JESD204 PHY

Is this cause ADS54J69 ?

Do you know what caused this error ?

Is there a workaround for this error ?

Best Regards,

Hiroshi Katsunaga

ADS8509: About wait time of PWRDL

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Part Number: ADS8509

Hello,

 

Regarding to wait time of PWRD on ADS8509, my customer is asking a question..

(Question)

When device is changed to normal power from low power by PWRD pin, how long should it wait for next conversion start?

                         

Regards,

Tao 2199

ADS1258: ads1258 spi driver

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Part Number: ADS1258

Can i get ads1258 driver source code for linux based architecture using spi-interface ?

ADS8588H: layout for the bypass capacitor

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Part Number: ADS8588H

Hi

Regarding the layout guideline, the bypass capacitors of AVDD and DVDD is mounted in the bottom layer as it's mentioned at the datasheet.

I understand it's best way to place the bypass capacitor at the bottom layer when we place the bypass capacitor as possible as close to IC.

But is there any recommend layout suggestion if it can not be placed the capacitor at the bottom layer? (The parts can not be placed at the bottom layer in the customer's PCB.)

Best Regards,

Koji Hamamoto

DAC8568: SOME PROBLEMS

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Part Number: DAC8568

Hi dear 

I have some problems with the dac8568 datasheet. 

1- what does mean the Grade A,B,C or D in the datasheet. is it an option when buying the device or a setting that we could change it?

2-what's the difference between flexible mode and static mode when we power up internal reference? in both of them we have the same options in the datasheet. it just difference in bit's we should send to shift register.

3- how can we choose synchronous or Asynchronous mode for load data?

4- what does "Update selected DAC registers" do in page 36 of datasheet? what's the different with writing to such a Register? the DACs are updated on the 32 falling edge of the SCLK or falling edge of /LDAC so what does this code do?

5- what's the different between 3 different power down mode? and if we want a channel to don't send any current for a short time period it's better to power down this channel or write 00000000 to this channel and if choosing power down, which mode is better for us?

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