Part Number: AMC7836
Dear team,
My customer likes the AMC7836 however they don't have any GPIOs available on their MCU.
Is it possible to use the device only with I2C interface (without using the AMC7836 GPIO) ?
Can they achieve full functionality using I2C only ?
Regards,
Nir.
Part Number: ADS131E08
Hello guys,
I am designing a project to measure 8 resistive strain gauge at the same time and values returned by SPI.
I plan to use the ADS131E08. Do you think this component can satisfy this need?
Thanks
Regards,
Damien
Part Number: ADS131E08
Hi,
my customer is multiplexing one channel of the ADC with analog switch to sample signal 1 and signal 2, is it okay to do that?
When we switch from signal 1 from signal 2, how long should we wait to start the conversion?
Any other consideration needs to be taken when multiplexing the signal?
Part Number: DATACONVERTERPRO-SW
We need to evaluate the ADC performance of as TI GSPS ADC in combination with the TSW14J56EVM/TSW14J57EVM and Data Converter Pro software.
Our tests require to analyze a huge variety of input signals, thus we need some automation of the Data Converter Pro software. It would be sufficient, if the software can be triggered to start a new aquisition and exports the acquired data to a file. All settings of the ADC remain unchanged and can be made manually via the GUI. We would just need a way to control this in an automated way, e.g., sending a byte to a TCP/UDP port or using an API. It could be even a hardware trigger sent to TSW14J56EVM board which would be most preferable, meaning a new recording file is generated whenever a trigger signal occurs (of course, I would ensure that enough time is in between two events as reading the data over USB3.0 and writing it to disk will take quite some time)
Is there any way to accomplish this with the software?
BTW: having this functionality in output direction (proving a DAC data file) and updating the DAC data in an automated way might be also a useful feature in near future for us.
Part Number: AFE4410EVM
Hi,
1. I am working on Rx_sup current consumption measurement with AFE4410EVM and AFE4410 GUI. However, the Rx_sup current is about 120uA @16hz sampling rate. Would you kindly tell me how to config the EVM to get consistent test results with its datasheet?
2. I want to know how to set the registers of AFE4410 to get into deep sleep mode because my sampling rate ranges only from 16hz -100hz.
BTW, you can also reply to me via email or a call. Please find my contact information via the infolink.
Best regards,
Shubiao Wang
Part Number: ADS4142
Hi Team,
Our customer has a slight clarification on the external RCR filter applied on the ADS4142EVM. I understand that this is to minimize input sampling glitches for low frequency operations. However, there is a slight discrepancy between the RCR filter resistor values of the ADS4142EVM (25Ω) and the typical driving circuit given on the ADS4142 datasheet (50Ω).
Can you give us insights on how the resistor filter values were set? Thank you very much.
Kind Regards,
Jejomar
Part Number: ADS8860
Hi there,
I ama learning TI Precision Lab Video on SAR ADC. On page 7 of PPT slide of section 5.1, it mentioned that "As mentioned previously the RC charge bucket does not act as an anti-aliasing filter, but it does help with noise.", as snapshot below, highlighted the last sentence.
I understand this RC charge bucket filter is designed to charge the Csh quickly as well as keep amplifier stable, also, it's cut-off freq. is often much higher than the freq. required by an Anti-Alias Filter (AAF) in my experience.
However , what should we do if we need an AAF? Inserting an addtional real AAF somewhere among the signal chain ? Hope some TI experts could help advice. Thanks!
Part Number: ADS1298ECGFE-PDK
I want to know that ASD1298 IC life-cycle.
Thank You.
Part Number: ADS1294
Hello,
I'm using an ADC1294 to pick up signals from a sodium chloride solution. For signals larger than 10 Milivolt this works without problems.
I would like to measure signals in the microvolt range and use a low-noise signal generator that can generate 20Hz signals with an amplitude of up to 130µV. Which settings do you recommend? I have currently set a gain factor of 12 and a data rate of 250SPS. Do you think a preamplifier is necessary? The measurements are carried out in a shielded chamber.
AVDD = 3.3V and DVDD = 1.8V
Many thanks in advance!
Jason
Part Number: DAC8750
Dear all,
I would like to ask about Rload in the following figure.
I have been asked by our customers how much Rload is acceptable.
The data sheet does not specifically describe the range of Rload, and only Rload = 300Ω is shown in the reference data.
What is the maximum allowable Rload?
Best Regards,
Y.Ottey
Part Number: ADS131M04
Hello,
ADS131MO4 provide two filter for output data, fast-settling filter and sinc3 filter. It has to take three data rate periods to get a precise result as the following code indicates:
Is there any to read an accurate result during each SYNC? My customer needs valid data at each SYNC.
Paul
Part Number: ADS1292R
I am trying to output the midrail reference [(AVDD+AVSS)/2], which should be 1.65V based on my 3.3V power.
To do so, I have connected the RLD_AMP to RLDREF_INT (reg 0Ah = 2) and disconnecting it from channel 1 and channel 2 (reg 06h = 32). In theory then, I should just be buffering the midrail voltage. I then route this signal to IN1P. I tried this on the ADS1299 and it worked fine (5Vdd, chan 2 outputs 2.5V when configured as above).
Instead of midrail however, I measure 3.3V at the output.
The feedback passives on the RLD amp are 1Mohm and 1nF (50V) - and all other relevant pathings are internal.
Thoughts?
Part Number: ADS1256
Hi Team,
I found “Table 17. Sample Crystals” as a CRYSTAL recommendation in the datasheet.
"MANUFACTURER FREQUENCY PARTNUMBER Citizen 7.68MHz CIA / 53383 "
Is the CIA / 53383 part number still available from the manufacturer?
If not, please tell me the current recommendation.
Best Regards,
Kenji
Part Number: ADS7952
Hello!
We have a board containing two ADS7952SDBT devices, and on about 1 in 10 boards we sometimes encounter an error with one, or occasionally both, ADCs immediately after power-up. On the remaining boards, despite numerous attempts to trigger this fault it never seems to occur.
We have narrowed down the failure mode to the device not always correctly processing the data on SDI in the first frame. In the first frame after power-up we shift in: Manual Mode, selecting channel 10 and 2xVREF input range. We repeat this same data on SDI for frames 2 and 3. In frame 3 we expect the data from channel 10 to be returned on SDO, along with the selected channel number. On some occasions the ADC returns channel number 0 in this frame. On other occasions the ADC correctly returns channel number 10, but it returns an ADC reading twice that expected.
This behaviour fits with the ADC not always correctly processing the ADC channel number and/or the input range bit in the first frame after power-up, and instead continuing to use the reset values given in the datasheet. All subsequent frames are processed correctly until the ADC is powered down and left long enough for all power rails to fully discharge. If we always got a correct reading or an ADC channel number of 0 returned then I could imagine the device was just completely missing the first frame. However, the fact it sometimes returns the correct channel number but uses the wrong input range makes it appear it is sometimes receiving at least part of the frame correctly.
This feels as though the device isn't being powered up cleanly, so what power sequence requirements are there? What are the minimum/maximum rise times for each of the rails and is there a maximum time for which the device can have only some of the power rails enabled? For example, should there be any issue with powering up +VA all the time, to avoid analogue inputs exceeding +VA, but then powering up and down +VBD and REFP?
We are powering up +VA to 5V, then +VBD to 3.3V before REFP to 2.5V. If we change the sequencing to bring +VBD up and the same time as +VA then the problem seems to disappear (we still need to do more testing to confirm this on multiple boards).
What other things might prevent the ADC from correctly processing the first SPI frame? We've checked all the analogue inputs and digital signals and can't see anything coming up before its corresponding power rail.
Any additional information about the device, or suggestions of other things to check would be gratefully received.
Thanks,
Rob
Part Number: ADS54J60EVM
Dear E2E,
Good day!
A customer of mine is looking for the schematic of ADS54J60EVM Rev C. Is this available? Also, may I know what are the differences between Rev C and Rev D?
Looking forward to your response.
Regards,
Fanz
Part Number: ADS1256
Dear Hall,
Christopher Hall (1528318) My adc working fine, but i have problems writing in the register yet still I'm able to get the converted data. Please check my previous comment. I got 3 questions to be addressed. Kindly help me with the same. waveshare adc
Question 1: The values which I'm writing in the status, adcon, drate registers doesn't match with the values which I read after 100ms in the same registers.
But the values which I write in the MUX register matches and I've verified it by varying dynamically. Kindly help me with the problem.
Question 2: The drate value defaults to 0xF0(since drate value is not updating when I write on it) which is 30ksps and I've verified that value with my drdy signal in an oscilloscope.
The problem is when I give an input as sinusoidal signal of frequency 1Hz(time period = 1sec) I get only 2.8k samples for a sec.
My assumption is that if I set as 30ksps then for a sine wave with time period of 1sec should get 30k samples, but when I read the samples I get only 2.8k samples. I've set my spi clock frequency is 2MHz. Please correct me if I wrong.
What should I do to achieve at least a minimum of 10k samples ?
Question 3: How to use RDATAC command? If possible share a snippet of your code that involves rdatac command. Should I check for the drdy signal to go now or will update automatically?
Part Number: ADS131M04
Hi TI support,
We are considering the ADS131M04 in our design.
Can you please help with the questions below
Q1) Does this device supports pseudo differential inputs?
INxP -> single-ended analog input centered at mid rail.
INxN -> mid rail
Q2) Can you advise on the WQFN package availability?
Thanks!
AJ
Part Number: ADS131A04EVM
Hi there, I am using the eval kit with an FPGA wired in as the master and am experiencing some trouble with the ADC not giving me data on the first DRDY falling edge. Then I don't see DRDY come back down low so I am wondering if I have a setting incorrect somewhere:
I have the following settings for asynchronous interrupt mode with +/-2.5V input voltage:
JP1: Installed to allow FPGA to be the master
I am using the USB power so left the JP2 and JP3 jumpers as is
JP5: 1-2: (M0: IOVDD Asynchronous interrupt mode)
JP6: 2-3 (M1 : GND 24 bit)
JP7: I tried both 2-3 and float and received same results. (M2 hamming code disable)
JP8: Uninstalled (Charge pump of)
JP9: Tried both installed and uninstalled. (use onboard reference)
JP10: Uninstalled (Use on board IOVDD)
JP11: 2-3 (Use +/-2.5V supplies)
I am using the following config process to enable the ADC for 4096 Oversampling to give me a 4KHZ sampling rate in asynchronous interrupt mode. Let me know if there is an incorrect setting in the CFG:
Send Null Command: 0x000000
Send Unlock Command: 0x065500
Send SYS_CFG_REG Write: 0x4B6800
Send CLK1_REG Write: 0x4D0000
Send CLK2_REG Write: 0x4D0000
Send ADC_EN Register Write: 0x4F0F00
Send Wakeup Command: 0x003300
Send Lock Register Command: 0x055500
Send Null Command: 0x000000 (I get every response up to here correct and you can see that in the logic analyzer shot)
Wait until the ADC pulls DRDY low and then go and read all the channel data. When I read the data, I get the Lock register command back as the status but flatlined DIN for the 4 channels of data. When I keep the ADC as is and reset the FPGA to restart the initialization routine, I and only then see the correct data from the ADC after DRDY goes low. Then after this read, I don't see DRDY come back low again.
This is the initialization:
This is the first data read:
Part Number: ADC12DJ5200RF
I'm using the ADC12DJ5200RF-EVM Rev B in JMODE3 to interface with a Stratix 10 FPGA. The receive side of the JESD link uses Intel JESD204B IP, which has worked when I used the ADC12DJ3200-EVM. I've gotten the link up, with K = 20, but I see bad data mixed with expected samples.
The images below show the data stream at the output of the Intel JESD204B Receiver IP, at the link clock rate, before (jesd_link_*_data) and after (tpl_data_*_out) the transport layer. These images were captured with no input stimulus, so I'd expect values near zero.
Signal Tap, pre and post transport layer:
Plotted, post-transport layer:
I'm thinking that maybe my external sample and reference clocks are bad, but both share a common 10 MHz reference and look mostly clean on a spectrum analyzer. My sample clock is 9 dBm and reference clock is 6 dBm. I'm not sure why this is happening, could it be the JESD204C protocol has extra alignment words periodically sent around the data?
Thanks,
Ryan
Part Number: THS5661A
Hi E2E,
Good day.
Just like to inquire if you have the HBM rating for THS5661A?
Information is not available on the datasheet.
Thanks in advance.
Art