Part Number: ADS7924
Hi
We could see Absolute Max Junction Temperature as 125degC.
Max operating temperature as 85degC.
What would be the Recommended Max Junction Temperature for this device?
Our board sees close to 95degC at near to this ADC.
What would be the power dissipation of this component when all the analog lines are loaded?
Kindly give your input on these two aspects.
Regards,
Felix.
Part Number: ADS1292R
On the ADS1292R to calibrate we first set the bit RESP2[7] = 1 to enable calibration and then issue the OFFSETCAL SPI command. After that is complete is there any reason to reset the RESP2[7] bit to 0? Can we just leave it at 1 forever or does it matter?
Thanks,
Dan
Part Number: ADS6424
we have connected ads6422 with input clock lvpecl level (80M) we have the device parallel configuration.
looking at dclk and pclk we 240M 20mv p2p and 80M 80mv p2p
these signal are connected to latice fpga.
clarification:
The same configuration was used with ads6422 and worked perfectly.
the difference was the input clock which was connected using 40M cmos level through the clock baloon configuration as described in the evb.
whay using the faster device we get such a week dclk and pclk ?
what can we do if we are using parallel configuration ?
Thanks
Jacob
Part Number: ADS127L01
We're using the ADS127L01 with a multiplexer. If we use the normal differential in, differential out adc driver like the THS4551 then I need a buffer between the mux and THS4551 so the on resistance of the mux doesn't affect signal level, so more space, cost, and noise is involved. Is there a way to drive the ADS127L01 using just a single part? Thanks
Part Number: AFE4300
Hello,
I am currently in the process of developing custom boards for the AFE4300 and I am having a lot of issues with interfacing it with my MCU.
This custom board has its SPI pins exposed for viewing and potentially interfacing with other AFE4300s. I have confirmed that the MCU on the custom board can interface with the AFE4300-EVM. How I confirmed this is I read from registers and I was able to confirm their default states. Plus, I was able to write to these registers and read back to confirm that the registers have changed. I was also able to do a weight scale simulation and I was able to read a change in data.
However, I tried interfacing the MCU on the custom board with three AFE4300 custom boards and they all have different issues.
The 1st AFE4300's MISO always responds with all 1's. And for some reason it doesn't have the ability to drive a 0 (confirmed by putting a pulldown on MISO).
The 2nd AFE4300's MISO always responds with constant 0.
The 3rd AFE4300's MISO works (I read from multiple registers and I was able to confirm their default states), however when I write to the registers, the registers stay at their default state when I read from them.
I know this is a tough problem to crack without actually being here in person, and it could just be that my custom board has hardware faults, but I was wondering if there is any way to debug this.
Part Number: TSW14J56EVM
Hello,
I got TSW14J56EVM REV E. But the FPGA firmware for Quartus in the webstie is designed for REV D. Can I apply REV D design to to REV E design? If no, can I get fpga firmware for rev E design.
Also, is it compatible with Quartus 18.0 version? Or only Quartus 14.0 is needed.
Thanks,
Part Number: ADS1293
Hi Sirs,
My customer can bring up the ADS1293 and capture ECG waveforms. The lead-off function works with RA LA LL and RL connected, but malfunction with no RL.
Would you please advise the hardware and software configurations to enable the lead-off function with RA LA LL with no RL connection?
Thank you and Best regards,
Wayne Chen
08/10/2019
Part Number: ADS41B49
Usually, the high-order adc is selected to obtain a higher effective number of bits and a better signal-to-noise ratio. However, in the actual selection process, the dynamic indicators of the same level of 12-bit adc and 14-bit adc are similar. The signal-to-noise ratio is similar, and some chips have the same performance, such as ads41b49 and ads41b29. The dynamic performance of these two adcs is exactly the same, but the price of 14-bit adc($72) is almost 12-bit adc ($38) Twice. So what are the advantages of a 14-bit adc compared to a 12-bit adc of the same type in performance or in practice so that the price can be much higher?
Part Number: ADS1262
Hello Sir,
I am new to this ADC.I want run my Hall sensor on this ADC.
Then, you have provide the excel software for ADS1262.
When I m using PGA gain as 1 and Vin(-)(differential input) = 0 then it is impossible for me to get full range of values forhall sensor.
As minimum value Vin(-) = 0.3V when gain is 1.
So, how to solve this problem?
Pranav K Moudgil
Part Number: ADS1261EVM
Hi,
I have a simple script to collect data on two different channels. I'd like to collect the data and visualize it / export it to a file.
I noticed that if I run the entre script, the display program only shows the first set of data.
If I step through the script, the first data graphed and is then overwritten by the second.
I'd like to collect both sets of data and visualize it / export it.
Is that possible?
Thanks,
D
My Script:
First set of data
Second set of data
Part Number: ADS1230
I am having a load-cell connected with ADS1230. ADS1230 is interfaced with 8bit STM8s controller. while operating system on 5V, ADS1230 is giving 0xFFFFF value, i'm not getting the conversion as per loadcell voltage changes. While operating on 3V3 voltage, everything is working fine. In my schematic I want to operate whole system on 5V instead of 3V3. I'm not getting what is going wrong.
I need to get it resolved as soon as possible. Any comments or guidance highly appreciated.
Part Number: DAC81416EVM
Good Morning,
This might be a very generic question, but I was wondering if it would be possible to program DAC81416 from the eval module using the Arduino IDE and their built-in SPI library.
Thank You
Part Number: DAC81416EVM
Hi, I have some problems with initiating this board. I have installed the software (GUI) from the TI website and make sure that my board is connected using USB2ANY.
Based on the manual, I connect the supply J7.3: GND, J7.4:5V, J7.5: 5V, J7.6: GND, J7.7:10V.
Then, I set the value by using the GUI,
SYNC:OFF, TOGGLE mode: OFF, DAC range: 0~5V, DIFF:OFF, LDAC: OFF, DEVPWRDWN: PW DWN
and I also set all the DAC value: FFF and make all the output on.
However, I cannot see any voltage output using the multi-meter.
I was wondering if someone can kindly give me some guidance to start using this board.
Thanks in advance
Part Number: ADS1281EVM-PDK
I follow the instruction manual, but I can not connect the ADS1281EVM-PDK to the computer.
Connected power + 10V, -10V, GND and +6V.
Jumpers are set by default. Installed only the program ADC Pro v.2.0.1
When connected to a USB it is defined as an unknown device ID "USB\VID_0451&PID_9001"
Windows7 64 bit.
Part Number: ADS1258
Hi,
Anybody Please Review our schematics and share your valuable feedback.
I have few Questions.
1.How to terminate unused ADC channels and GPIO Lines, currently we are using only 8 ADC Channels.
2.external crystal has 70K series Resistance ,it is ok or we need to change the Different crystal.
3.AVSS and DGND we are using same GND.it is correct or we need to maintain separate GNDs.
Part Number: DAC38J84
Dear TI Supporters,
The DAC38J84 SerDes PLL is not locking in our system. Will you help diagnose the problem?
We are integrating Abaco FMC144 with an Intel Arria 10 SoC Dev Kit.
There is no reference design; we have developed our code by referring to the DAC3XJ8X GUI v1.2 (in simulation mode) and the BSP made available by Abaco.
Our application operates the four converters independently.
The DAC38J84 DACCLK input is driven correctly, because the FPGA measures other DCLKoutX outputs at the desired frequency, and all DCLKoutX outputs are programmed at the same frequency.
The FPGA receives the expected SYSREF pulse train, as captured in signaltap.
Here are the key parameters:
LMFS: 4421
Sample rate: 148.5Msps
Ext CLK; bypass (disable/reset) DAC PLL
SYSREF: 2 pulses @ 1/32 DACCLK frequency
Interpolation: 1
Serdes linerate: 2970Mbps
K: 32
serdes clk div: 1
jesd clk div: 1
SerDes rate: 1/4
SerDes MPY: 20
Here is the DAC385J84 configuration sequence:
bool DAC_init(void)
{
bool allOK = TRUE;
alt_u16 reg_value;
// Step numbers are from Kang Hsia's adaptation of slaa696
// Step 4, toggle DAC_RESETB (manual sec 8.3 Step 5)
system_control_write(DEV, DEV_DAC_TXENABLE, FALSE); // make sure TX is disabled until after JESD_init()
system_control_write(DEV, DEV_DAC_RESET, TRUE); // toggle RESETb (inverted on the way to the pin in top-level verilog)
usleep(1); // ensure RESETb pulse width exceeds 25ns minimum
system_control_write(DEV, DEV_DAC_RESET, FALSE);
Send_DAC(0x02,0x2083); // [15:14] 16-bit DAC width, [13] zero invalid data, [7] enable SPI_DAC_SDO, [1] 2's complement, [0] = assert soft reset
Send_DAC(0x02,0x2082); // [15:14] 16-bit DAC width, [13] zero invalid data, [7] enable SPI_DAC_SDO, [1] 2's complement, [0] = clr soft reset
// Step 5, confirm PoR presets have loaded
reg_value = Read_DAC(0x7f);
if ((bit_field(reg_value, DAC_LOAD_STATUS, DAC_LOAD_STATUS) == 1)
&& (bit_field(reg_value, DAC_VENDOR_HI, DAC_VENDOR_LO) == DAC_VENDOR_ID)
&& (bit_field(reg_value, DAC_VERSION_HI, DAC_VERSION_LO) == DAC_VERSION_ID)) {
rubydbprint(DBSS_DAC,"DAC chip fusefarm loaded correctly.\r\n");
} else {
allOK = FALSE;
rubydbprint(DBSS_DAC,"DAC chip fusefarm failed to load, reading back error code %x, vendor code %u, version %u.\r\n",
bit_field(reg_value, DAC_ERR_CODE_HI, DAC_ERR_CODE_LO),
bit_field(reg_value, DAC_VENDOR_HI, DAC_VENDOR_LO),
bit_field(reg_value, DAC_VERSION_HI, DAC_VERSION_LO));
}
// Step 6, "program per application's need"
// Step 6.0 housekeeping not addressed in Kang's sequence
Send_DAC(0x4A,0x0f1e); // Hold the JESD state machine in reset during programming (not per Kang's sequence, but Abaco does this as the very 1st thing)
Send_DAC(0x04,0xf0f0); // [11:8] are lanes 3..0 SerDes lane errors and [3:0] are lanes 3..0 FIFO flags; mask the others
Send_DAC(0x05,0xef05); // mask SYSREF errors from unused links, (unused) PAP alarms, SerDes block 1, and unused DAC PLL
Send_DAC(0x06,0xffff); // mask all short tests and LOS alarms
Send_DAC(0x23,0xffff); // allow all subsystems to sleep when SLEEP is asserted (for live shutdown)
// Step 6.1, Clocking Configuration Registers: DAC PLL (unused): regs 0x31 to 0x33
Send_DAC(0x1A,0x0020); // [5] DAC PLL sleep
Send_DAC(0x24,0x0000); // [6:4] = 0 SYSREF pulses don't reset dividers, because DAC PLL is unused
Send_DAC(0x31,0x1000); // [12] = 1 PLL reset; [10] = 0 PLL disable (in favor of direct DACCLK to the core)
// Step 6.2, SerDes PLL and PMAs regs 0x3B to 0x3F
Send_DAC(0x3B,0x0000); // [15] bypass internal PLL, use DACCLK input as SerDes refclk; [14:11] divide refclk by 1
// Send_DAC(0x3C,0x18a0); // SerDes PLL [15] !EN div by 5 output; [12:11] high loop bandwidth; [10] !sleep; [9] = 0 high VCO freq. range; [8:1] MPY = 20
// Send_DAC(0x3C,0x00a0); // SerDes PLL [15] !EN div by 5 output; [12:11] medium loop bandwidth, per Abaco; [10] !sleep; [9] = 0 high VCO freq. range; [8:1] MPY = 20
Send_DAC(0x3C,0x10a0); // SerDes PLL [15] !EN div by 5 output; [12:11] low loop bandwidth, for poor clock; [10] !sleep; [9] = 0 high VCO freq. range; [8:1] MPY = 20
Send_DAC(0x3D,0x0088); // [7] EN offset compensation; [5] no EQ boost; [4:3] = 1 adaptive EQ; [2:0] = 0 for CDR algorithm 0
Send_DAC(0x3E,0x0148); // [15:13]: no LOS alarm in any lane; [10:8]: AC coupled termination; [6:5]: 1/4 rate; [4:2]: 20b 8b10b double-word width; [1]: !Sleep RX ccts
// Step 6.3, JESD204B parameters incl configuring JESD RX FSM regs 0x46 to 0x62
// Leave the Lane ID per PoR, at the risk of lane configuration errors, to avoid potentially confusing the receiver
// Send_DAC(0x46,0x0000); // set Lane ID to 0 for lanes 0 .. 2, to avoid JESD ILAS errors
// Send_DAC(0x47,0x010a); // set Lane ID to 0 for lane 3
Send_DAC(0x25,0x0000); // JESD clock rate == input clock rate
Send_DAC(0x4B,0x1f01); // both coded N+1: [12:8] elastic read buffer depth = 32 (== K); [7:0] 2 octets per SerDes frame (== F)
Send_DAC(0x4C,0x1f03); // both coded N+1: [12:8] JESD K = 32; [4:0] L = 4 lanes in use
Send_DAC(0x4D,0x0300); // both coded N+1: [15:8] M = 4 converters per link; [4:0] selects S = 1 sample per frame (@ 2 octets, that means 16b samples)
Send_DAC(0x4F,0x1c41); // [7] = 0 do not match a specific symbol, begin buffering the 1st non-K after ILAS completes; [0] = 1 enable JESD comma align
Send_DAC(0x51,0x00df); // [7:0] enable any of the errors to generate a sync request, except link configuration
Send_DAC(0x52,0x00df); // [7:0] enable any of the errors to count, except link configuration
Send_DAC(0x61,0x0001); // only link0 drives SYNCb
// Step 6.4, DSP blocks, all of the substantive ones bypassed.
// Step 6.4.a regs 0x00 to 0x02
Send_DAC(0x22,0x1be4); // [15:8] implement direct input correspondence; [7:0] implement output swizzle
Send_DAC(0x00,0x0018); // [15:12] disable analog functions; [11:8] interpolation = 1; [4:3] enable alarm out @ positive polarity
// [7],[5] don't disable outputs on alarm; [6] don't sum datapaths; [2:0] disable power amp protection & inv sync filters
// Reg 0x02 was initialised at the outset rather than here, to provide for SPI readback
// Step 6.4.b respective coefficients from regs 0x08 to 0x19
// ... all of the blocks controlled by these coefficients are bypassed
// Step 6.4.c DSP block initializers are set from regs 0x1E to 0x20
// ... all of the blocks controlled by these coefficients are bypassed
// Step 7, Verify SerDes PLL Lock Status
usleep(1000); // wait before testing PLL lock (Kang's lock acquisition interval calculation at the bottom of Step 7 implies ~20usec for 148.5MHz)
Send_DAC(0x6C,0x0000); // clear alarms
usleep(200);
reg_value = Read_DAC(0x6C); // test alarm_rw0_pll, confirm SERDES PLL is locked
if (bit_field(reg_value, DAC_SERDES_PLL_LOCK_ALARM, DAC_SERDES_PLL_LOCK_ALARM)) { // DAC_SERDES_PLL_LOCK_ALARM is position [3]
printf("DAC chip SerDes PLL is out of lock.\r\n");
allOK = FALSE;
}
else printf("DAC chip SerDes PLL is locked to DACCLK.\r\n");
// The remaining Steps initialisation Steps appear in DAC_JESD_arm() and DAC_JESD_disarm()
return allOK;
} // DAC_init
Would you kindly advise as to why the SerDes PLL is not locking?
Hopeful thanks --todd
Part Number: AFE0064
Hi there,
In the datasheet it specifies that the integrator's positive input voltage is 1.68V
However, the reset levels are either REFM or REFP (depending on up/down integration). I f I understood correctly, the integrator should be able to use the complete ABS(REFP-REFM) voltage range for the output.
How can this be the case if the OA positive input voltage is 1.68V? Is the integrating capacitor discharged completely during reset? or is it preset to REFM/REFP?
Thank you very much in advance!
Part Number: ADS1282
Hi,
I'm planning on using ADS1282 on an Eval board, in bipolar mode for Gain Cal, I plan to use +/-2.5V on VREFP/N & +/- 2.5V on AVDD/AVSS. (Vref = VREFP – VREFN) which should be Vref = 2.5 - (-2.5) =5V with PGA =1, is that correct ?
In Bipolar mode with a 5V Vref (as above) for gain cal must supply input signal pins should be +1.25V to INP and - 1.25V to INN that correct? +/-Vref/(2*1) = 2.5/2 = 1.25V
in Unipolar I plan to have 5V on VREFP & 0V on VREFN, is that ok?
Thanks, Chris.
Part Number: ADS131A04
Hi,
i am struggling with initialization of ADC.
I use 24Bits, no Hammingcode, no CRC. I did this steps and i mean that until point 3 all is OK.
| step | Command | 1.Byte | 2.Byte | 3.Byte | Response on MISO | |
| 1 | NULL | 0x00 | 0x00 | 0x00 | 0xFF04 | |
| 2 | UNLOCK | 0x06 | 0x55 | 0x00 | 0x0655 | |
| 3 | WAKEUP | 0x00 | 0x33 | 0x00 | 0x0033 | |
| 4 | WREG | 0x0F | 0x0F | 0x00 | ??? |
But after step 4 i got different values on MISO pin.
Are this steps right?
Part Number: DAC3482
Hi team,
My customer is using our DAC3482 in a signal generator project. We measured the spectrum of the output signal and found there are side band signals around.
Test condition:
1. input clk=500MHz, PLL=2 so DACCLK=1GHz
2. Datarate=500Msps, interpolation=2 so sample rate=1Gsps.
3. NCO is shutdown
When we set the output signal frequency to 10MHz, the spectrum is as below: The central frequency(maker 1)=10MHz, -20.169dBm. The side band signal (maker 3/maker 2) is=10.008MHz, -72.958dBm / 10.017MHz, -77.146dBm
When we set the output signal frequency to 20MHz, the spectrum is as below: The side band signal is=20.008MHz, -68.069dBm / 20.017MHz, -72.019dBm
So can you help analyze why the side band signal will show up and how to get rid of it? Thanks.
Best regards,
Wayne