Part Number: ADS131M04
I have tried a couple of PDF readers before asking if the Figures 81 through 84 are identical in the datasheet version "SBAS890A–MARCH 2019–REVISED JULY 2019". I am on Alert Me if the datasheet is revised.
Thank you
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ADS131M04: Data sheet Figure 81 through 84
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ADC12D1800RF: HDL Model
Part Number: ADC12D1800RF
Hi Team,
My Customer is designing with existing FPGA source to communicate to our ADC12D1800RF, but he'd like to have a simulation environment with a TI supplied HDL model that he can simulate against. Does something like this exist?
Regards,
-Renan
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ADS1231: ADS1231 Read jitter
Part Number: ADS1231
HI Sir
I want to design a weight scale module,which use the ADS1231
because i don't have the load cell now,so i input the standard voltage to the ADC input,
but i found the mcu reading is jitter
the sw is on/ off swith by scope
but i install the standard load cell, the reading is stable
Please advise it.thanks
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AFE4900： The relationship between the internal clock and the startup voltage, and the error range of the internal clock
Part Number: AFE4900
I use the internal 128khz clock and set the PRF to 25, but I found that the output frequency is wrong. When the starting voltage is different, the output frequency is different, 3.0v-37ms, 3.3v-45ms, the correct value should be 40ms. Is it caused by inaccurate internal clock or other factors. Choosing an external clock can be cumbersome for hardware reasons
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DAC0800: EOL Plan
Part Number: DAC0800
Hi,
Our customer is considering replacing the competitive product with DAC0800. So, are you planning to be EOL for DAC0800 ?
Best regards,
Kato
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ADS1258: Register configuration and hardware connectivity issues in fixed channel mode
Part Number: ADS1258
Hi, ADS1258 provides me an option of AUTO SCAN mode and also Fixed Channel Mode.
And I am using the "Fixed Channel mode" to read a particular channel, my understanding looking at the Data sheet is that I need to follow the below mentioned steps to set the channels in fixed channel mode:
- Send the command byte to select the register CONFIG 0 and set the bit "MUXMOD" to 1
- Send a command to select the register "MUXSCH"
My question here is how do I select "One particular channel" using the register "MUXSCH", and whether my schematic design is wrong？
I set CONFIG0 = 0x32, CONFIG1 = 0x02, MUXSCH = 0x01, for example, to select AIN0 as the positive input and AIN1 as the negative input, and AIN1 has tied to GND, but no valid data is returned.
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VSP5610: What voltage should i get on REFP AND REFN
Part Number: VSP5610
Hi,
Can you please know me what voltage should i get on
REFP with respect to ground?
REFN with respect to ground?
And REFP-REFN?
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CCS/AFE4410: calculate SpO2
Part Number: AFE4410
Tool/software: Code Composer Studio
I want to calculate the SpO2 value after after the calibration, but I don't know whether the offsetDAC and Gain value is accurate.
Whether new procedures are needed to estimate their values?
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ADS8166: Replace from AD7689 to ADS8166
Part Number: ADS8166
Dear Technical Support Team,
I'm investigating to replace from AD7689 to ADS8166.
Are there any advantage compared to AD7689?
General specs are already checked such as SINAD and THD and so on.
I'd like to improve linearity and gain error.
Your advise is useful for me.
Best Regards,
ttd
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DAC8760: problem with two devices in spi daisy-chain
Part Number: DAC8760
I have 2 DAC8760 devices connected in daisy-chain, the 2 are configured in 10 volts of output,
the first one is correct, but the second does not exceed 3 volts.
its the same configuraration,i send in 48 bits frame , but only the first works.
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ADC12DL3200: LVDS output interface synchronization?
Part Number: ADC12DL3200
I use an ADC12DL3200 in a project. I choose to single sample and 4 LVDS outputs mode. ADC clock is provided by a LMK04828 at 1.2GHz, which also provide a clock of 300MHz to FPGA. In FPGA, I use 4 FIFOs to collect 4 LVDS path data with seperate path dclk, then read the FIFO data with 300MHz clock provided by LMK04828. However, these 4 path fifos' output data is not always aligned. I do not know where is the problem?
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ADS1278EVM-PDK: semi-Standalone mode, using Motherboard power supply: J4 isolation?
Part Number: ADS1278EVM-PDK
I have the ADS1278EVM on top of the modular motherboard (MMB0, Rev D).
I need to interface the EVM to an FPGA via J4 for control and J2 for the 8 serial data channels, using it in SPI mode, low-power mode, with 4.096 MHz input clock, 16.0 KSPS serial output (digital audio).
I would like to keep the EVM connected to the MMB0 thru all three headers (J3, J4, J5) for mechanical stability and to take advantage of the MMB0 power supply (J5), but otherwise use the EVM in standalone mode.
It looks like the analog input EVM/J3 pins (which go to MMB0/J10) are sufficiently isolated; i.e., not driven or loaded by the motherboard.
But I can't tell if the control pins on EVM J4 are sufficiently isolated (not driven by MMB0 J4) to directly connect my FPGA to EVM J4.
I have a Rev C. MMB0 schematic (could not find Rev D), which shows much of J4 being isolated by the FET switch U4 when U4/DCEN = 1, which I'm guessing is the default value unless an I2C write from the MMB0 processor changes it.
But I don't know if I can guarantee the processor won't eventually enable MMB0/U4, or if other pins on MMB0/J4 that aren't connected to MMB0/U4 are sufficiently isolated.
Note: I don't plan to use the ADC-Pro software in this configuration, or have the MMB0 processor do anything other than its normal background/idle stuff.
On EVM/J4, I need to drive
MODE[1:0] = "10" (pins 6,2), (but will omit these if it is safe to set non-default values on DIP switch S2).
FORMAT[2:0] = "010" (pins 14,12,8), (but will omit these if it is safe to set non-default values on DIP switch S2).
SYNCn = "1" (pin 1),
CLKSEL = "0" (pin 19),
CLK = 4.096 MHz (pin 17),
and receive
SCLK = 512 KHz (pin 3),
DRDYn = 16.0 KHz (pin 15).
I don't (think I) care about CLKR (pin 5), FSX (pin 7), FSR (pin 9), Dx (pin 11), DR (pin 13), SCL (pin 16), or SDA (pin 20) since I'm using SPI mode and not outputting the modulator clock.
THE QUESTIONS:
1. For the above scenario, do I need to completely isolate EVM/J4 from MMB0/J4 (e.g., clip the pins off MMB0/J4 so they don't conflict with my FPGA drive & receive)?
1a. If so, do we lose the pull-up resistors from MMB0 that keep the SCL & SDA pins from floating (as inputs to EVM U7, U8, and U14), and if so, would this be a problem?
2. Can I safely use the DIP switches on S2 for FORMAT[2:0] and MODE[1:0] instead of driving them with my FPGA?
3. Can I safely set the DIP switches on S1 to POWER-UP all 8 ADC channels? If the I2C port expanders are only reading these pins (never trying to write them), there should be no conflict.
4. The EVM-PDK User's Guide (SBAU197A–February 2012–Revised January 2016) in Section 5.6 (Power Supply Header, J5) states,
The ADS1278 digital supplies are connected as follows:
• IOVDD supply is connected to the +1.8VD pin of the J3 header.
• DVDD supply is connected to the +3.3VD pin of the J3 header.
Are the two bullets above backward? Everything on the EVM and MB schematics suggest a 1.8v core voltage (DVDD) and 3.3v I/O voltage (IOVDD); in particular, MMB0 (Rev. C) schematic shows
J5/7 = +1.8VD (EVM J5/7 = DVDD)
J5/9 = +3.3VD (EVM J5/9 = IOVDD)
Thanks very much!
MarkJ
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ADS1675: tradeoff to reduce power consumption? Rbias resistor at for 25Mhz?
Part Number: ADS1675
Team,
The ADS1675 would be interesting for a project but the nominal power consumption is too high.
-Are there ways to reduce the power consumption significantly? What would be the tradeoff?
In the same condition the consumption is much higher than the ADS127L01.
-For a clock speed of 25Mhz:
What Rbias resistor values can be used? is 30k OK? What would be the impacts on the performances?
Datasheet only answers for 8, 16 and 32Mhz.
-What is the input impedance of the ADC? Do we have information to dimension the anti-aliasing filter?
Thanks in advance!
A.
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DAC80508: Using an external reference with the DAC80508
Part Number: DAC80508
Originally asked in this thread:https://e2e.ti.com/support/data-converters/f/73/t/836424
Moving this question to a new thread
Andrzej asked: "
How to connect external reference voltage to this DAC since its output is as default also configured as output?
In DAC8568 chip the internal reference was disabled by default."
Paul: "we anticipated the case where the user wants to use an external reference. The reference current capability is fairly low (±5mA), so during startup, the internal reference and your external reference will conflict with each other but only with this low current. The DAC will either sink or source current depending on the voltage of the external reference. As long as the abs max table is not being violated, there will not be any damage. This conflicted state will exist until the reference is disabled."
Andrzej: "In regards to the reference. It is very strange and unusual solution to connect output to output.
especially given the fact that external source of reference voltage is unknown
e.g. it may be very strong output of OPA or super precision/delicate/expensive external reference voltage source."
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AMC7932
(Please visit the site to view this file)
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DAC8563: EMC/EMI/RFI Issues
Part Number: DAC8563
I have a new sensor design using the DAC8563 chip. The DAC output signals (VoutA, VoutB) are fine until I begin the RFI/EMC immunity tests.
When the DUT is subjected to an RF power of 10V/meter, the DAC output voltages shift. During an RF sweep of 80 - 250 Mhz, this voltage shift shows up at various frequencies & amplitudes. The worst-case shift error is as much as 35 millivolts at 123 Mhz.. Other analog and digital circuits on the PCB do not seem to be affected by the RF field. The power supplies and Vref output pin are steady & clean.
I have tried various PCB and cabinet grounding configurations, ferrite beads, shielding etc., but the voltage error is still present. This problem looks like the RF rectification that sometimes shows up in op-amps and instrumentation amps when subjected to an RF field.
Has anybody seen this problem with a DAC?
Thanks, Alan
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MSP432/ADS1292R: Problems with ADS1292R interaction
Part Number: ADS1292R
Tool/software: Code Composer Studio
Hello friends,
I need some help to create a interface between the MSP432 and ADS1292R. I have speend a lot of time trying to connect
this chip, with this microcontroler and I can t get successefull proccess . I have decide, and I have done a small code to try
interact with chip, but sommething has wrong.
Soo, my friends does anyone with a lot o knowledge have a chip from the MSP430 familly, if someone have had any interface with these devices, I appreciate your help or ability to share.
Attached I send the code I made, hoping that someone will help me analyze and can help correct.
Thanks in advance
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)
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ADS1298: Voltage of RLD amplifier at Rail
Part Number: ADS1298
Hello,
I have a problem with the RLD of the ADS 1298. My RLD is derived from ch1+ and Ch1- of the ADS1298. The output of my RLD is at the rail 3V.
While the voltage on RLDINV is at 1.25V where 1.5V is expected . I have set RLDREF internally to be at mid-rail. I am running on a 3V battery supply. I am using preamplifer for ECG acquisition where the rails are 0V to 3V. If RLD is at 3V out I wouldn't get any signal. I have using a 1pF and 1Mohm feedback resistor and capacitor between RLD inv and RLD out. I have tried shorting the 1mohm resistor in this cause RLD inv is 1.5V but there would be no feedback through the input electrodes. I have also removed the preamplifers and this problem still exists.
Thanks
Amrit
Amrit
G:\My Drive\SKIIN\Product Development\1. Hardware Development\Electronics\Other Projects\Holter Baby Band
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TLV1548-Q1: SPI I/O CLK activity during sample conversion
Part Number: TLV1548-Q1
Hello, I have a question regarding the SPI I/O CLK during the conversion step. Is it required that the CLK be active? The timing diagrams in the DS (for example Figure 16) suggest this is the case, as compared to the CS line. Is it allowable for the CLK to be off such as in the case where the SPI transfer width is only 10-bits?
Thanks
Bill
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ADS1278EVM-PDK: EVM connection to FPGA question
Part Number: ADS1278EVM-PDK
I have the ADS1278EVM on top of the modular motherboard (MMB0, Rev D).
I need to interface the EVM to an FPGA via J4 for control and J2 for the 8 serial data channels, using it in SPI mode, low-power mode, with 4.096 MHz input clock, 16.0 KSPS serial output (digital audio).
I would like to keep the EVM connected to the MMB0 thru all three headers (J3, J4, J5) for mechanical stability and to take advantage of the MMB0 power supply (J5), but otherwise use the EVM in standalone mode.
It looks like the analog input EVM/J3 pins (which go to MMB0/J10) are sufficiently isolated; i.e., not driven or loaded by the motherboard.
But I can't tell if the control pins on EVM J4 are sufficiently isolated (not driven by MMB0 J4) to directly connect my FPGA to EVM J4.
I have a Rev C. MMB0 schematic (could not find Rev D), which shows much of J4 being isolated by the FET switch U4 when U4/DCEN = 1, which I'm guessing is the default value unless an I2C write from the MMB0 processor changes it.
But I don't know if I can guarantee the processor won't eventually enable MMB0/U4, or if other pins on MMB0/J4 that aren't connected to MMB0/U4 are sufficiently isolated.
Note: I don't plan to use the ADC-Pro software in this configuration, or have the MMB0 processor do anything other than its normal background/idle stuff.
On EVM/J4, I need to drive
MODE[1:0] = "10" (pins 6,2), (but will omit these if it is safe to set non-default values on DIP switch S2).
FORMAT[2:0] = "010" (pins 14,12,8), (but will omit these if it is safe to set non-default values on DIP switch S2).
SYNCn = "1" (pin 1),
CLKSEL = "0" (pin 19),
CLK = 4.096 MHz (pin 17),
and receive
SCLK = 512 KHz (pin 3),
DRDYn = 16.0 KHz (pin 15).
I don't (think I) care about CLKR (pin 5), FSX (pin 7), FSR (pin 9), Dx (pin 11), DR (pin 13), SCL (pin 16), or SDA (pin 20) since I'm using SPI mode and not outputting the modulator clock.
THE QUESTIONS:
1. For the above scenario, do I need to completely isolate EVM/J4 from MMB0/J4 (e.g., clip the pins off MMB0/J4 so they don't conflict with my FPGA drive & receive)?
1a. If so, do we lose the pull-up resistors from MMB0 that keep the SCL & SDA pins from floating (as inputs to EVM U7, U8, and U14), and if so, would this be a problem?
2. Can I safely use the DIP switches on S2 for FORMAT[2:0] and MODE[1:0] instead of driving them with my FPGA?
3. Can I safely set the DIP switches on S1 to POWER-UP all 8 ADC channels? If the I2C port expanders are only reading these pins (never trying to write them), there should be no conflict.
4. The EVM-PDK User's Guide (SBAU197A–February 2012–Revised January 2016) in Section 5.6 (Power Supply Header, J5) states,
The ADS1278 digital supplies are connected as follows:
• IOVDD supply is connected to the +1.8VD pin of the J3 header.
• DVDD supply is connected to the +3.3VD pin of the J3 header.
Are the two bullets above backward? Everything on the EVM and MB schematics suggest a 1.8v core voltage (DVDD) and 3.3v I/O voltage (IOVDD); in particular, MMB0 (Rev. C) schematic shows
J5/7 = +1.8VD (EVM J5/7 = DVDD)
J5/9 = +3.3VD (EVM J5/9 = IOVDD)
Thanks very much!
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